Graphical framework for automatic generation of custom UVM testbenches in SystemVerilog applied for the validation of a SerDes DUT
A novel graphical tool designed to assist Pre-Silicon validators in the creation of complete, functional, and compile-clean UVM testbenches is presented in this case study. A detailed description of the user-friendly interface is documented and demonstrated to auto-generate a validation environment...
| Autores: | , |
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| Tipo de recurso: | tesis de maestría |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2021 |
| País: | México |
| Institución: | Instituto Tecnológico y de Estudios Superiores de Occidente |
| Repositorio: | Repositorio Institucional del ITESO |
| Idioma: | inglés |
| OAI Identifier: | oai:rei.iteso.mx:11117/6521 |
| Acceso en línea: | https://hdl.handle.net/11117/6521 |
| Access Level: | acceso abierto |
| Palabra clave: | SystemVerilog UVM Verification Validation Serdes Framework Testbench Code Generator |
| Sumario: | A novel graphical tool designed to assist Pre-Silicon validators in the creation of complete, functional, and compile-clean UVM testbenches is presented in this case study. A detailed description of the user-friendly interface is documented and demonstrated to auto-generate a validation environment template for the verification of an ALU and SerDes chip. The output obtained from the tool is later customized and optional sections are filled up to perform the full validation of the circuit. For the SerDes DUT, this case study takes over from the work of the latest 2017 ITESO SerDes circuit design. Both authors of this document worked on the 2016 iteration and are very familiar with the design, but this time instead of the actual design of the chip, the primary focus is how this new validation tool can be an essential asset to ensure the quality of the chip and to improve the efficiency of the verification process. |
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