Rivas-Villegas, R., & Limones-Mora, C. F. (2021). Graphical framework for automatic generation of custom UVM testbenches in SystemVerilog applied for the validation of a SerDes DUT.
Citación estilo ChicagoRivas-Villegas, Rogelio, y César F. Limones-Mora. Graphical Framework for Automatic Generation of Custom UVM Testbenches in SystemVerilog Applied for the Validation of a SerDes DUT. 2021.
Cita MLARivas-Villegas, Rogelio, y César F. Limones-Mora. Graphical Framework for Automatic Generation of Custom UVM Testbenches in SystemVerilog Applied for the Validation of a SerDes DUT. 2021.
Precaución: Estas citas no son 100% exactas.