Parameterizable OoO core verification using UVM
This thesis aims to develop the verification environment of a highly parameterizable RISC-V superscalar Out-of-Order (OoO) processor called Lagarto OX, developed for high performance computing (HPC) applications. It is part of the Spanish Proyectos Estratégicos para la Recuperación y Transformación...
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| Formato: | tesis de maestría |
| Fecha de publicación: | 2025 |
| País: | España |
| Recursos: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/450798 |
| Acesso em linha: | https://hdl.handle.net/2117/450798 |
| Access Level: | acceso embargado |
| Palavra-chave: | Computer architecture RISC microprocessors SystemVerilog RTL Processor RISC-V OoO Superscalar Functional verification Test validation Coverage Simulation UVM Verilator Open-source Verification Arquitectura d'ordinadors Microprocessadors RISC Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Resumo: | This thesis aims to develop the verification environment of a highly parameterizable RISC-V superscalar Out-of-Order (OoO) processor called Lagarto OX, developed for high performance computing (HPC) applications. It is part of the Spanish Proyectos Estratégicos para la Recuperación y Transformación Económica (PERTE) Chip initiative project led by the Barcelona Supercomputing Center (BSC), whose objective is to strengthen the design and production capabilities of the microelectronics and semiconductor industry in Spain through the development of a family of processors. In this thesis, the Lagarto OX verification environment is extended from previous BSC work done on a processor verification environment called Core-UVM. Core-UVM is a modular and parameterizable environment that performs test validation using a co-simulation approach. The resulting environment has been able to find multiple bugs in the Register Transfer Level (RTL) design under test (DUT) and obtaining great coverage metrics, while maintaining the compatibility with the rest of the PERTE family of processors and adding new features such as compatibility with Verilator, an open-source RTL simulation tool. |
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