Ionizing radiation damage in 65 nm CMOS technology: influence of geometry, bias and temperature at ultra-high doses

We studied the radiation response of 3 different 65 CMOS planar technologies at the ultra-high doses expected to be reached in the HL-LHC, the upgraded large hadron collider of CERN. All the processes studied are sensitive to radiation and show similar degradation mechanisms and, albeit with differe...

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Autores: Borghello, G., Lerario, E., Faccio, F., Koch, H.D., Termo, G., Michelis, S., Márquez Lasso, F.J., Palomo Pinto, Rogelio, Muñoz Chavero, Fernando
Tipo de recurso: artículo
Estado:Versión aceptada para publicación
Fecha de publicación:2021
País:España
Institución:Universidad de Sevilla (US)
Repositorio:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/168068
Acceso en línea:https://hdl.handle.net/11441/168068
https://doi.org/10.1016/j.microrel.2020.114016
Access Level:acceso abierto
Palabra clave:65 nm CMOS technology total ionizing dose
Ultra-high doses
MOSFET reliability
High luminosity-large hadron collider
Spacers
Shallow trench isolation
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spelling Ionizing radiation damage in 65 nm CMOS technology: influence of geometry, bias and temperature at ultra-high dosesBorghello, G.Lerario, E.Faccio, F.Koch, H.D.Termo, G.Michelis, S.Márquez Lasso, F.J.Palomo Pinto, RogelioMuñoz Chavero, Fernando65 nm CMOS technology total ionizing doseUltra-high dosesMOSFET reliabilityHigh luminosity-large hadron colliderSpacersShallow trench isolationWe studied the radiation response of 3 different 65 CMOS planar technologies at the ultra-high doses expected to be reached in the HL-LHC, the upgraded large hadron collider of CERN. All the processes studied are sensitive to radiation and show similar degradation mechanisms and, albeit with different intensities, similar dependencies on device geometry, applied polarization and temperature. The results obtained confirmed that the performance of MOS transistors exposed to ultra-high doses is mainly affected by radiation-induced charge trapped in auxiliary oxides such as shallow trench isolation oxides and spacers. The extensive data collected has been used to develop guidelines to qualify to ultra-high doses ASICs designed in the 65 technology node.ElsevierIngeniería ElectrónicaTIC192: Ingeniería Electrónica2021info:eu-repo/semantics/articleinfo:eu-repo/semantics/acceptedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/168068https://doi.org/10.1016/j.microrel.2020.114016reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésMicroelectronics Reliability, 116, 114016.https://www.sciencedirect.com/science/article/pii/S0026271420309033info:eu-repo/semantics/openAccessoai:idus.us.es:11441/1680682026-06-17T12:51:07Z
dc.title.none.fl_str_mv Ionizing radiation damage in 65 nm CMOS technology: influence of geometry, bias and temperature at ultra-high doses
title Ionizing radiation damage in 65 nm CMOS technology: influence of geometry, bias and temperature at ultra-high doses
spellingShingle Ionizing radiation damage in 65 nm CMOS technology: influence of geometry, bias and temperature at ultra-high doses
Borghello, G.
65 nm CMOS technology total ionizing dose
Ultra-high doses
MOSFET reliability
High luminosity-large hadron collider
Spacers
Shallow trench isolation
title_short Ionizing radiation damage in 65 nm CMOS technology: influence of geometry, bias and temperature at ultra-high doses
title_full Ionizing radiation damage in 65 nm CMOS technology: influence of geometry, bias and temperature at ultra-high doses
title_fullStr Ionizing radiation damage in 65 nm CMOS technology: influence of geometry, bias and temperature at ultra-high doses
title_full_unstemmed Ionizing radiation damage in 65 nm CMOS technology: influence of geometry, bias and temperature at ultra-high doses
title_sort Ionizing radiation damage in 65 nm CMOS technology: influence of geometry, bias and temperature at ultra-high doses
dc.creator.none.fl_str_mv Borghello, G.
Lerario, E.
Faccio, F.
Koch, H.D.
Termo, G.
Michelis, S.
Márquez Lasso, F.J.
Palomo Pinto, Rogelio
Muñoz Chavero, Fernando
author Borghello, G.
author_facet Borghello, G.
Lerario, E.
Faccio, F.
Koch, H.D.
Termo, G.
Michelis, S.
Márquez Lasso, F.J.
Palomo Pinto, Rogelio
Muñoz Chavero, Fernando
author_role author
author2 Lerario, E.
Faccio, F.
Koch, H.D.
Termo, G.
Michelis, S.
Márquez Lasso, F.J.
Palomo Pinto, Rogelio
Muñoz Chavero, Fernando
author2_role author
author
author
author
author
author
author
author
dc.contributor.none.fl_str_mv Ingeniería Electrónica
TIC192: Ingeniería Electrónica
dc.subject.none.fl_str_mv 65 nm CMOS technology total ionizing dose
Ultra-high doses
MOSFET reliability
High luminosity-large hadron collider
Spacers
Shallow trench isolation
topic 65 nm CMOS technology total ionizing dose
Ultra-high doses
MOSFET reliability
High luminosity-large hadron collider
Spacers
Shallow trench isolation
description We studied the radiation response of 3 different 65 CMOS planar technologies at the ultra-high doses expected to be reached in the HL-LHC, the upgraded large hadron collider of CERN. All the processes studied are sensitive to radiation and show similar degradation mechanisms and, albeit with different intensities, similar dependencies on device geometry, applied polarization and temperature. The results obtained confirmed that the performance of MOS transistors exposed to ultra-high doses is mainly affected by radiation-induced charge trapped in auxiliary oxides such as shallow trench isolation oxides and spacers. The extensive data collected has been used to develop guidelines to qualify to ultra-high doses ASICs designed in the 65 technology node.
publishDate 2021
dc.date.none.fl_str_mv 2021
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/acceptedVersion
format article
status_str acceptedVersion
dc.identifier.none.fl_str_mv https://hdl.handle.net/11441/168068
https://doi.org/10.1016/j.microrel.2020.114016
url https://hdl.handle.net/11441/168068
https://doi.org/10.1016/j.microrel.2020.114016
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv Microelectronics Reliability, 116, 114016.
https://www.sciencedirect.com/science/article/pii/S0026271420309033
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Elsevier
publisher.none.fl_str_mv Elsevier
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,812429

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