Ionizing radiation damage in 65 nm CMOS technology: influence of geometry, bias and temperature at ultra-high doses
We studied the radiation response of 3 different 65 CMOS planar technologies at the ultra-high doses expected to be reached in the HL-LHC, the upgraded large hadron collider of CERN. All the processes studied are sensitive to radiation and show similar degradation mechanisms and, albeit with differe...
| Autores: | , , , , , , , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2021 |
| País: | España |
| Institución: | Universidad de Sevilla (US) |
| Repositorio: | idUS. Depósito de Investigación de la Universidad de Sevilla |
| OAI Identifier: | oai:idus.us.es:11441/168068 |
| Acceso en línea: | https://hdl.handle.net/11441/168068 https://doi.org/10.1016/j.microrel.2020.114016 |
| Access Level: | acceso abierto |
| Palabra clave: | 65 nm CMOS technology total ionizing dose Ultra-high doses MOSFET reliability High luminosity-large hadron collider Spacers Shallow trench isolation |
| Sumario: | We studied the radiation response of 3 different 65 CMOS planar technologies at the ultra-high doses expected to be reached in the HL-LHC, the upgraded large hadron collider of CERN. All the processes studied are sensitive to radiation and show similar degradation mechanisms and, albeit with different intensities, similar dependencies on device geometry, applied polarization and temperature. The results obtained confirmed that the performance of MOS transistors exposed to ultra-high doses is mainly affected by radiation-induced charge trapped in auxiliary oxides such as shallow trench isolation oxides and spacers. The extensive data collected has been used to develop guidelines to qualify to ultra-high doses ASICs designed in the 65 technology node. |
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