Optimization of Continuous-Time Pipeline ADC Architectures for Wideband Medium-Resolution Applications
Continuous-time pipeline (CT-Pipeline) ADCs are an emerging analog-to-digital medium-resolution converter architecture. Recently demonstrated examples prove that they are capable of achieving larger bandwidths than those of state-of-the-art continuous-time ΣΔ ADCs, which until now were the preferred...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2025 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/429986 |
| Acceso en línea: | https://hdl.handle.net/2117/429986 |
| Access Level: | acceso abierto |
| Palabra clave: | Analog-to-digital converters Integrated circuits--Computer-aided design ADC Pipeline Convertidors analògic/digitals Circuits integrats--Disseny assistit per ordinador Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
| Sumario: | Continuous-time pipeline (CT-Pipeline) ADCs are an emerging analog-to-digital medium-resolution converter architecture. Recently demonstrated examples prove that they are capable of achieving larger bandwidths than those of state-of-the-art continuous-time ΣΔ ADCs, which until now were the preferred wideband mediumresolution ADC choice. In this work, this type of converter is demonstrated through a MATLAB Simulink model. Throughout these pages, a detailed analysis and explanation of this topology is provided, while proposing solutions to some of the recurring design challenges. With regard to the implementation, the use of power-efficient VCO quantizers has been evaluated. A comparison is also conducted between two alternatives for the digital reconstruction filter. In addition, the most common non-idealities and their effects are also introduced and validated by simulation. The developed model of a 4-stage continuous-time pipeline ADC achieves a SNDR of 80 dB over a 400-MHz bandwidth. It is intended to serve as an initial step towards the implementation of a CT-Pipeline that achieves an SNDR of 70 dB. |
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