Design of a 12-bit ramp ADC in 250 nm for image sensor ICs
This thesis presents the design of a 12-bit single slope ADC embedded in an image sensor integrated circuit (IC) that takes advantage of the signal-dependent photon-shot noise characteristic inherent in image sensors. It is implemented using a column ADC architecture and incorporates a digital doubl...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2023 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/402437 |
| Acceso en línea: | https://hdl.handle.net/2117/402437 |
| Access Level: | acceso embargado |
| Palabra clave: | Analog-to-digital converters Integrated circuits ADC IC CMOS Single Slope Convertidors analògic/digitals Circuits integrats Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència |
| Sumario: | This thesis presents the design of a 12-bit single slope ADC embedded in an image sensor integrated circuit (IC) that takes advantage of the signal-dependent photon-shot noise characteristic inherent in image sensors. It is implemented using a column ADC architecture and incorporates a digital double sampling technique for removing the possible non-linearities. The circuit has been thoroughly studied and designed from a theoretical standpoint, and the performance and robustness of each sub-block have been ensured under various PVT and Montecarlo simulations. Finally, the layout of the analog domain of the ADC column has been completed in a 250nm CMOS process |
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