Towards automated analog design verification: a case study on the design, layout and automated verification of an op-amp in a 12nm FinFET technology using script-based, EDA tool-agnostic PVT analysis
The verification of analog circuits at advanced technology nodes poses significant challenges due to Process, Voltage, and Temperature (PVT) variations, LayoutDependent Effects (LDEs), and parasitics. Traditional manual verification is timeconsuming, error-prone, and often insufficient for robust pe...
| Autor: | |
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2025 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/452523 |
| Acceso en línea: | https://hdl.handle.net/2117/452523 |
| Access Level: | acceso abierto |
| Palabra clave: | Analog integrated circuits Integrated circuits--Verification Electronic circuit design Analog design FinFETs Automation Verification PVT corners Circuits integrats analògics Circuits integrats--Verificació Circuits electrònics--Disseny i construcció Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
| Sumario: | The verification of analog circuits at advanced technology nodes poses significant challenges due to Process, Voltage, and Temperature (PVT) variations, LayoutDependent Effects (LDEs), and parasitics. Traditional manual verification is timeconsuming, error-prone, and often insufficient for robust performance assessment. This thesis presents a script-based, Electronic Design Automation (EDA) toolagnostic framework for automated PVT verification of analog circuits, demonstrated on a two-stage operational amplifier implemented in 12 nm FinFET technology. The amplifier was designed and laid out to meet its basic specifications, serving as a practical learning vehicle rather than an optimized tape-out-ready design. The framework integrates post-layout parasitic extraction, deterministic corner sweeps, and automated performance reporting, while allowing design specifications to be provided as script inputs for flexible and repeatable checks. The results highlight the impact of parasitics and layout-induced variations, while offering a flexible foundation for further automation and adaptation to other analog designs. This work contributes a practical, modular approach to improving analog verification efficiency, accuracy, and reproducibility in modern nanometer-scale technologies. |
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