On the optimal placement of on-chip decaps in std-cell designs, for PSN reduction at a given place. Versió 1
This report concerns to the optimal placement of decaps in digital circuits to decrease the PSN at the point where noise sensitive circuits (as PLLs, for instance) are located. The question is generally answered in a practical way: the decaps should placed as close as possible of the noise sources (...
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| Tipo de recurso: | informe técnico |
| Fecha de publicación: | 2008 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/441864 |
| Acceso en línea: | https://hdl.handle.net/2117/441864 |
| Access Level: | acceso abierto |
| Palabra clave: | Decoupling capacitors (decaps) Power Supply Noise (PSN) Optimal placement Power Distribution Network (PDN) Àrees temàtiques de la UPC::Enginyeria electrònica Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència |
| Sumario: | This report concerns to the optimal placement of decaps in digital circuits to decrease the PSN at the point where noise sensitive circuits (as PLLs, for instance) are located. The question is generally answered in a practical way: the decaps should placed as close as possible of the noise sources (big buffers, flip-flops…) but evidence to sustain such affirmation is not conclusive or it is not proved. Several publications addresses this topic [1] and their results seem to confirm the same conclusion. However, such conclusion is extracted from experiments at chip level, that is, on circuits and environments too complex to reveal which parameters determine the optimal placement of decaps and why. This topic, from our knowledge, has not been never analyzed from a theoretical point of view and so it needs to be addressed to discover what are the key factors to determine the optimal placement of decaps. The purpose of the present note is to analyze this topic on a circuit model that collects the main circuit features, as placement of the current sources and decaps, impedance of the PDN, circuit dimensions, and so on. Such model, yet complete, should be simple enough to admit an analytical treatment to extract simple rules for design. In addition, the rules must be checked by electrical simulations on more realistic digital circuits. |
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