A CMOS test chip for PSN mesurements (general description). Draft
In a previous Research Report [1], a method to estimate the Power Supply Noise in the supply distribution network of a digital circuit was described. Such method was validated by electrical simulation of small parts of the circuit but and no experimental validation was obtained. However, such experi...
| Autores: | , |
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| Tipo de recurso: | informe técnico |
| Fecha de publicación: | 2007 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/441861 |
| Acceso en línea: | https://hdl.handle.net/2117/441861 |
| Access Level: | acceso abierto |
| Palabra clave: | Power supply noise Power distribution network (PDN) Integrated circuit (IC) Experimental validation Àrees temàtiques de la UPC::Enginyeria electrònica Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència |
| Sumario: | In a previous Research Report [1], a method to estimate the Power Supply Noise in the supply distribution network of a digital circuit was described. Such method was validated by electrical simulation of small parts of the circuit but and no experimental validation was obtained. However, such experimental work is needed in order to adjust the parameters used in the method and to check the range of error that has the method compared with real silicon due to its simplifications and assumptions. This is the motivation of the design of the present test chip. The aim of this project is the design of an integrated circuit (IC) to enable the experimental study of the noise at the power distribution network (PDN) of a digital circuit as a function of the temporal and spatial distribution of its activity. |
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