Hot-carrier degradation in deep-submicrometer nMOSFETs: Lightly doped drain vs. large angle tilt implanted drain

The hot-carrier degradation of lightly doped drain (LDD) and large angle tilt implanted drain (LATID) nMOSFETs of a0.35 μm CMOS technology is analysed and compared by means of I-V characterisation and charge pumping current measurements. LATID nMOSFETs are found to exhibit a significant improvement...

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Detalhes bibliográficos
Autores: Rafí, Joan Marc, Campabadal, Francesca
Formato: artículo
Fecha de publicación:2001
País:España
Recursos:Consejo Superior de Investigaciones Científicas (CSIC)
Repositorio:DIGITAL.CSIC. Repositorio Institucional del CSIC
OAI Identifier:oai:digital.csic.es:10261/256996
Acesso em linha:http://hdl.handle.net/10261/256996
https://api.elsevier.com/content/abstract/scopus_id/0035416660
Access Level:acceso abierto
Palavra-chave:Hot carrier reliability | Hot carriers | LATID | LDD | MOSFET
id ES_bbe2a787d8ef2e4ce79a91a65273f72f
oai_identifier_str oai:digital.csic.es:10261/256996
network_acronym_str ES
network_name_str España
repository_id_str
spelling Hot-carrier degradation in deep-submicrometer nMOSFETs: Lightly doped drain vs. large angle tilt implanted drainRafí, Joan MarcCampabadal, FrancescaHot carrier reliability | Hot carriers | LATID | LDD | MOSFETThe hot-carrier degradation of lightly doped drain (LDD) and large angle tilt implanted drain (LATID) nMOSFETs of a0.35 μm CMOS technology is analysed and compared by means of I-V characterisation and charge pumping current measurements. LATID nMOSFETs are found to exhibit a significant improvement in terms of both, current drivability and hot-carrier immunity at maximum substrate current condition. The different factors which can be responsible for this improved hot-carrier resistance are investigated. It is shown that this must be attributed to a reduction of the maximum lateral electric field along the channel, but not to a minor generation of physical damage for a given electric field or to a reduced I-V susceptibility to a given amount of generated damage. Further to this analysis, the hot-carrier degradation comparison between LDD and LATID devices is extended to the whole range of gate-stress regimes and the effects of short electron injection (SEI) and short hole injection (SHI) phases on hot- carrier-stressed devices are analysed. Apart from a significant improved resistance to hot-carrier effects registered for LATID devices, a similar behaviour is observed for the two types of architectures. In this way, SEI phases are found to be an efficient tool for revealing part of the damage generated in stresses at low gate voltages, whereas the performance of a first SHI phase after stress at high gate bias is found to result in a significant additional degradation of the devices. This enhanced degradation is attributed to a sudden interface states build-up occurring in both, LDD and LATID devices, near the Si/spacer interface only under the first hot-hole injection condition. © 2001 Elsevier Science Ltd. All rights reserved.Peer reviewed0000-0003-4581-9477Consejo Superior de Investigaciones Científicas [https://ror.org/02gfc7t72]202120212001info:eu-repo/semantics/articlehttp://purl.org/coar/resource_type/c_6501http://hdl.handle.net/10261/256996https://api.elsevier.com/content/abstract/scopus_id/0035416660reponame:DIGITAL.CSIC. Repositorio Institucional del CSICinstname:Consejo Superior de Investigaciones Científicas (CSIC)InglésSolid-State Electronicshttps://doi.org/10.1016/S0038-1101(01)00004-1Síinfo:eu-repo/semantics/openAccessoai:digital.csic.es:10261/2569962026-05-22T06:33:51Z
dc.title.none.fl_str_mv Hot-carrier degradation in deep-submicrometer nMOSFETs: Lightly doped drain vs. large angle tilt implanted drain
title Hot-carrier degradation in deep-submicrometer nMOSFETs: Lightly doped drain vs. large angle tilt implanted drain
spellingShingle Hot-carrier degradation in deep-submicrometer nMOSFETs: Lightly doped drain vs. large angle tilt implanted drain
Rafí, Joan Marc
Hot carrier reliability | Hot carriers | LATID | LDD | MOSFET
title_short Hot-carrier degradation in deep-submicrometer nMOSFETs: Lightly doped drain vs. large angle tilt implanted drain
title_full Hot-carrier degradation in deep-submicrometer nMOSFETs: Lightly doped drain vs. large angle tilt implanted drain
title_fullStr Hot-carrier degradation in deep-submicrometer nMOSFETs: Lightly doped drain vs. large angle tilt implanted drain
title_full_unstemmed Hot-carrier degradation in deep-submicrometer nMOSFETs: Lightly doped drain vs. large angle tilt implanted drain
title_sort Hot-carrier degradation in deep-submicrometer nMOSFETs: Lightly doped drain vs. large angle tilt implanted drain
dc.creator.none.fl_str_mv Rafí, Joan Marc
Campabadal, Francesca
author Rafí, Joan Marc
author_facet Rafí, Joan Marc
Campabadal, Francesca
author_role author
author2 Campabadal, Francesca
author2_role author
dc.contributor.none.fl_str_mv 0000-0003-4581-9477
Consejo Superior de Investigaciones Científicas [https://ror.org/02gfc7t72]
dc.subject.none.fl_str_mv Hot carrier reliability | Hot carriers | LATID | LDD | MOSFET
topic Hot carrier reliability | Hot carriers | LATID | LDD | MOSFET
description The hot-carrier degradation of lightly doped drain (LDD) and large angle tilt implanted drain (LATID) nMOSFETs of a0.35 μm CMOS technology is analysed and compared by means of I-V characterisation and charge pumping current measurements. LATID nMOSFETs are found to exhibit a significant improvement in terms of both, current drivability and hot-carrier immunity at maximum substrate current condition. The different factors which can be responsible for this improved hot-carrier resistance are investigated. It is shown that this must be attributed to a reduction of the maximum lateral electric field along the channel, but not to a minor generation of physical damage for a given electric field or to a reduced I-V susceptibility to a given amount of generated damage. Further to this analysis, the hot-carrier degradation comparison between LDD and LATID devices is extended to the whole range of gate-stress regimes and the effects of short electron injection (SEI) and short hole injection (SHI) phases on hot- carrier-stressed devices are analysed. Apart from a significant improved resistance to hot-carrier effects registered for LATID devices, a similar behaviour is observed for the two types of architectures. In this way, SEI phases are found to be an efficient tool for revealing part of the damage generated in stresses at low gate voltages, whereas the performance of a first SHI phase after stress at high gate bias is found to result in a significant additional degradation of the devices. This enhanced degradation is attributed to a sudden interface states build-up occurring in both, LDD and LATID devices, near the Si/spacer interface only under the first hot-hole injection condition. © 2001 Elsevier Science Ltd. All rights reserved.
publishDate 2001
dc.date.none.fl_str_mv 2001
2021
2021
dc.type.none.fl_str_mv info:eu-repo/semantics/article
http://purl.org/coar/resource_type/c_6501
format article
dc.identifier.none.fl_str_mv http://hdl.handle.net/10261/256996
https://api.elsevier.com/content/abstract/scopus_id/0035416660
url http://hdl.handle.net/10261/256996
https://api.elsevier.com/content/abstract/scopus_id/0035416660
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv Solid-State Electronics
https://doi.org/10.1016/S0038-1101(01)00004-1
Sí
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.source.none.fl_str_mv reponame:DIGITAL.CSIC. Repositorio Institucional del CSIC
instname:Consejo Superior de Investigaciones Científicas (CSIC)
instname_str Consejo Superior de Investigaciones Científicas (CSIC)
reponame_str DIGITAL.CSIC. Repositorio Institucional del CSIC
collection DIGITAL.CSIC. Repositorio Institucional del CSIC
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869418064905240576
score 15,812429

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