Hot-carrier degradation in deep-submicrometer nMOSFETs: Lightly doped drain vs. large angle tilt implanted drain
The hot-carrier degradation of lightly doped drain (LDD) and large angle tilt implanted drain (LATID) nMOSFETs of a0.35 μm CMOS technology is analysed and compared by means of I-V characterisation and charge pumping current measurements. LATID nMOSFETs are found to exhibit a significant improvement...
| Autores: | , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2001 |
| País: | España |
| Institución: | Consejo Superior de Investigaciones Científicas (CSIC) |
| Repositorio: | DIGITAL.CSIC. Repositorio Institucional del CSIC |
| OAI Identifier: | oai:digital.csic.es:10261/256996 |
| Acceso en línea: | http://hdl.handle.net/10261/256996 https://api.elsevier.com/content/abstract/scopus_id/0035416660 |
| Access Level: | acceso abierto |
| Palabra clave: | Hot carrier reliability | Hot carriers | LATID | LDD | MOSFET |
| Sumario: | The hot-carrier degradation of lightly doped drain (LDD) and large angle tilt implanted drain (LATID) nMOSFETs of a0.35 μm CMOS technology is analysed and compared by means of I-V characterisation and charge pumping current measurements. LATID nMOSFETs are found to exhibit a significant improvement in terms of both, current drivability and hot-carrier immunity at maximum substrate current condition. The different factors which can be responsible for this improved hot-carrier resistance are investigated. It is shown that this must be attributed to a reduction of the maximum lateral electric field along the channel, but not to a minor generation of physical damage for a given electric field or to a reduced I-V susceptibility to a given amount of generated damage. Further to this analysis, the hot-carrier degradation comparison between LDD and LATID devices is extended to the whole range of gate-stress regimes and the effects of short electron injection (SEI) and short hole injection (SHI) phases on hot- carrier-stressed devices are analysed. Apart from a significant improved resistance to hot-carrier effects registered for LATID devices, a similar behaviour is observed for the two types of architectures. In this way, SEI phases are found to be an efficient tool for revealing part of the damage generated in stresses at low gate voltages, whereas the performance of a first SHI phase after stress at high gate bias is found to result in a significant additional degradation of the devices. This enhanced degradation is attributed to a sudden interface states build-up occurring in both, LDD and LATID devices, near the Si/spacer interface only under the first hot-hole injection condition. © 2001 Elsevier Science Ltd. All rights reserved. |
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