Synthesis of timing paths with delays adaptable to integrated circuit variability

This project proposes to substitute the Clock of a circuit for a Ring Oscillator. This Ring Oscillator is designed to be susceptible to variability in the same way than the rest of the system, allowing to drastically reduce variability guard band margins at design stage.

Detalles Bibliográficos
Autor: Moreno Vega, Alberto|||0000-0001-8133-0068
Tipo de recurso: tesis de maestría
Fecha de publicación:2015
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/81051
Acceso en línea:https://hdl.handle.net/2117/81051
Access Level:acceso abierto
Palabra clave:Integrated circuits
variabilitat
camí crític
process corner
beam search
ring oscillator
rellotges adaptatius
llibreria de standard cells
Variability
critical path
adaptive clocks
standard cell library
Circuits integrats
Àrees temàtiques de la UPC::Informàtica
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network_acronym_str ES
network_name_str España
repository_id_str
spelling Synthesis of timing paths with delays adaptable to integrated circuit variabilityMoreno Vega, Alberto|||0000-0001-8133-0068Integrated circuitsvariabilitatcamí críticprocess cornerbeam searchring oscillatorrellotges adaptatiusllibreria de standard cellsVariabilitycritical pathprocess corneradaptive clocksstandard cell libraryCircuits integratsÀrees temàtiques de la UPC::InformàticaThis project proposes to substitute the Clock of a circuit for a Ring Oscillator. This Ring Oscillator is designed to be susceptible to variability in the same way than the rest of the system, allowing to drastically reduce variability guard band margins at design stage.Universitat Politècnica de CatalunyaCortadella, Jordi20152015-07-1020152015-12-23master thesishttp://purl.org/coar/resource_type/c_bdccNAhttp://purl.org/coar/version/c_be7fb7dd8ff6fe43info:eu-repo/semantics/masterThesisapplication/pdfhttps://hdl.handle.net/2117/81051reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/810512026-05-27T15:37:01Z
dc.title.none.fl_str_mv Synthesis of timing paths with delays adaptable to integrated circuit variability
title Synthesis of timing paths with delays adaptable to integrated circuit variability
spellingShingle Synthesis of timing paths with delays adaptable to integrated circuit variability
Moreno Vega, Alberto|||0000-0001-8133-0068
Integrated circuits
variabilitat
camí crític
process corner
beam search
ring oscillator
rellotges adaptatius
llibreria de standard cells
Variability
critical path
process corner
adaptive clocks
standard cell library
Circuits integrats
Àrees temàtiques de la UPC::Informàtica
title_short Synthesis of timing paths with delays adaptable to integrated circuit variability
title_full Synthesis of timing paths with delays adaptable to integrated circuit variability
title_fullStr Synthesis of timing paths with delays adaptable to integrated circuit variability
title_full_unstemmed Synthesis of timing paths with delays adaptable to integrated circuit variability
title_sort Synthesis of timing paths with delays adaptable to integrated circuit variability
dc.creator.none.fl_str_mv Moreno Vega, Alberto|||0000-0001-8133-0068
author Moreno Vega, Alberto|||0000-0001-8133-0068
author_facet Moreno Vega, Alberto|||0000-0001-8133-0068
author_role author
dc.contributor.none.fl_str_mv Cortadella, Jordi
dc.subject.none.fl_str_mv Integrated circuits
variabilitat
camí crític
process corner
beam search
ring oscillator
rellotges adaptatius
llibreria de standard cells
Variability
critical path
process corner
adaptive clocks
standard cell library
Circuits integrats
Àrees temàtiques de la UPC::Informàtica
topic Integrated circuits
variabilitat
camí crític
process corner
beam search
ring oscillator
rellotges adaptatius
llibreria de standard cells
Variability
critical path
process corner
adaptive clocks
standard cell library
Circuits integrats
Àrees temàtiques de la UPC::Informàtica
description This project proposes to substitute the Clock of a circuit for a Ring Oscillator. This Ring Oscillator is designed to be susceptible to variability in the same way than the rest of the system, allowing to drastically reduce variability guard band margins at design stage.
publishDate 2015
dc.date.none.fl_str_mv 2015
2015-07-10
2015
2015-12-23
dc.type.none.fl_str_mv master thesis
http://purl.org/coar/resource_type/c_bdcc
NA
http://purl.org/coar/version/c_be7fb7dd8ff6fe43
dc.type.openaire.fl_str_mv info:eu-repo/semantics/masterThesis
format masterThesis
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/81051
url https://hdl.handle.net/2117/81051
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Universitat Politècnica de Catalunya
publisher.none.fl_str_mv Universitat Politècnica de Catalunya
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869414003829112832
score 15.301603

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