Synthesis of timing paths with delays adaptable to integrated circuit variability
This project proposes to substitute the Clock of a circuit for a Ring Oscillator. This Ring Oscillator is designed to be susceptible to variability in the same way than the rest of the system, allowing to drastically reduce variability guard band margins at design stage.
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2015 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/81051 |
| Acceso en línea: | https://hdl.handle.net/2117/81051 |
| Access Level: | acceso abierto |
| Palabra clave: | Integrated circuits variabilitat camí crític process corner beam search ring oscillator rellotges adaptatius llibreria de standard cells Variability critical path adaptive clocks standard cell library Circuits integrats Àrees temàtiques de la UPC::Informàtica |
| Sumario: | This project proposes to substitute the Clock of a circuit for a Ring Oscillator. This Ring Oscillator is designed to be susceptible to variability in the same way than the rest of the system, allowing to drastically reduce variability guard band margins at design stage. |
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