Physical implementation and verification of a multi-phase clock system
This thesis focuses on the physical design and verification of a multi-phase clock system, beginning with the provided analog circuit schematic of a ring oscillator. The primary objective is to optimize the layout, emphasizing minimal parasitics while adhering to Design Rule Check (DRC) and Layout v...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2024 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/420931 |
| Acceso en línea: | https://hdl.handle.net/2117/420931 |
| Access Level: | acceso embargado |
| Palabra clave: | Analog integrated circuits Oscillations Semiconductors multi-phase clock system analog circuit ring oscillator physical design verification parasitics DRC LVS semiconductor design layout optimization Circuits integrats analògics Oscil·lacions Àrees temàtiques de la UPC::Física::Física de l'estat sòlid::Semiconductors |
| Sumario: | This thesis focuses on the physical design and verification of a multi-phase clock system, beginning with the provided analog circuit schematic of a ring oscillator. The primary objective is to optimize the layout, emphasizing minimal parasitics while adhering to Design Rule Check (DRC) and Layout versus Schematic (LVS) rules. Strategic placement and routing techniques are explored to enhance the circuit's performance. The study highlights a meticulous approach to compliance, ensuring the design meets regulatory standards. The insights gained contribute to semiconductor design, offering practical solutions for complex analog circuit implementation. This work advances the understanding of multi-phase clock systems, emphasizing efficiency and reliability in physical design. |
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