Individual flip-flops with gated clocks for low power datapaths
Energy consumption has become one of the important factors in digital systems, because of the requirement to dissipate this energy in high-density circuits and to extend the battery life in portable systems such as devices with wireless communication capabilities. Flip-flops are one of the most ener...
| Autores: | , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 1997 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/129522 |
| Acceso en línea: | https://hdl.handle.net/2117/129522 https://dx.doi.org/10.1109/82.592586 |
| Access Level: | acceso abierto |
| Palabra clave: | Logic circuits Microprocessors -- Energy consumption Flip-flops Clocks Energy consumption CMOS technology Digital systems Batteries Wireless communication Power system modeling Circuit simulation Registers Circuits lògics Microprocessadors -- Consum d'energia Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
| Sumario: | Energy consumption has become one of the important factors in digital systems, because of the requirement to dissipate this energy in high-density circuits and to extend the battery life in portable systems such as devices with wireless communication capabilities. Flip-flops are one of the most energy-consuming components of digital circuits. This paper presents techniques to reduce energy consumption by individually deactivating the clock when flip-flops do not have to change their value. Flip-flop structures are proposed and selection criteria given to obtain minimum energy consumption. The structures have been evaluated using energy models and validated by switch-level simulations. For the applications considered, significant energy reductions are achieved. |
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