Energy macro-model for on chip interconnection buses
This report presents a fast method of evaluating the power consumption of a bus. Given an on-chip bus driver-interconnection-receiver design of N parallel lines,the objective is to develop its energy consumption macro-model. With this model we are be able to evaluate the energy metrics for the bus u...
| Autores: | , , , |
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| Tipo de recurso: | informe técnico |
| Fecha de publicación: | 2006 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/1232 |
| Acceso en línea: | https://hdl.handle.net/2117/1232 |
| Access Level: | acceso abierto |
| Palabra clave: | Microprocessors digital integrated circuits crosstalk power consumption leakage current circuits integrats - cmos Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Processadors digitals |
| Sumario: | This report presents a fast method of evaluating the power consumption of a bus. Given an on-chip bus driver-interconnection-receiver design of N parallel lines,the objective is to develop its energy consumption macro-model. With this model we are be able to evaluate the energy metrics for the bus under a certain traffic and information coding. |
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