Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability
With continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the L1 data cache tolerates wide process variations with little performance degrada...
| Autores: | , , |
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| Formato: | artículo |
| Fecha de publicación: | 2008 |
| País: | España |
| Recursos: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/121204 |
| Acesso em linha: | https://hdl.handle.net/2117/121204 https://dx.doi.org/10.1109/MM.2008.12 |
| Access Level: | acceso abierto |
| Palavra-chave: | Memory management (Computer science) Microprocessors Cache memory Cache storage DRAM chips Microprocessor chips SRAM chips System-on-chip Transistors Gestió de memòria (Informàtica) Microprocessadors Memòria cau Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Resumo: | With continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the L1 data cache tolerates wide process variations with little performance degradation, making it a promising choice for on-chip cache structures for next-generation microprocessors. |
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