Exploiting narrow values for soft error tolerance
Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper we propose simple mechanisms that effectively reduce the vulne...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2006 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/102025 |
| Acceso en línea: | https://hdl.handle.net/2117/102025 https://dx.doi.org/10.1109/L-CA.2006.12 |
| Access Level: | acceso abierto |
| Palabra clave: | Microprocessors Cache memory Error correction Process design Impurities Neutrons Cache storage Random access memory Hardware Manufacturing Multithreading Microprocessadors Memòria cau Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Sumario: | Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper we propose simple mechanisms that effectively reduce the vulnerability to soft errors in a processor. Our designs are generally motivated by the fact that many of the produced and consumed values in the processors are narrow and their upper order bits are meaningless. Soft errors canted by any particle strike to these higher order bits can be avoided by simply identifying these narrow values. Alternatively soft errors can be detected or corrected on the narrow values by replicating the vulnerable portion of the value inside the storage space provided for the upper order bits of these operands. We offer a variety of schemes that make use of narrow values and analyze their efficiency in reducing soft error vulnerability of level-1 data cache of the processor. |
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