Implementing a hybrid SRAM / eDRAM NUCA architecture
In this paper, we propose a hybrid cache architecture that exploits the main features of both memory technologies, speed of SRAM and high density of eDRAM. We demonstrate, that due to the high locality found in emerging applications, a high percentage of data that enters to the on-chip last-level ca...
| Autores: | , , , |
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| Tipo de recurso: | informe técnico |
| Fecha de publicación: | 2010 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/13932 |
| Acceso en línea: | https://hdl.handle.net/2117/13932 |
| Access Level: | acceso abierto |
| Palabra clave: | SRAM chips NUCA cache eDRAM module DRAM chips Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Sumario: | In this paper, we propose a hybrid cache architecture that exploits the main features of both memory technologies, speed of SRAM and high density of eDRAM. We demonstrate, that due to the high locality found in emerging applications, a high percentage of data that enters to the on-chip last-level cache are not accessed again before they are replaced |
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