Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation

This paper presents a simple but accurate semi-empirical model especially focused on 65 nm MOST (MOS transistor) technologies and radio-frequency (RF) applications. It is obtained by means of simple dc and noise simulations extracted over a constrained set of MOSTs. The fundamental variable of the m...

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Detalles Bibliográficos
Autores: Fiorelli, Rafaella, Peralías Macías, Eduardo
Tipo de recurso: artículo
Estado:Versión aceptada para publicación
Fecha de publicación:2016
País:España
Institución:Universidad de Sevilla (US)
Repositorio:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/74308
Acceso en línea:https://hdl.handle.net/11441/74308
https://doi.org/10.1016/j.vlsi.2015.07.018
Access Level:acceso abierto
Palabra clave:MOS transistor
gm/ID
Semi-empirical
RF
Nanometer technology
65 nm CMOS
Inversion level
CS-LNA
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oai_identifier_str oai:idus.us.es:11441/74308
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repository_id_str
spelling Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validationFiorelli, RafaellaPeralías Macías, EduardoMOS transistorgm/IDSemi-empiricalRFNanometer technology65 nm CMOSInversion levelCS-LNAThis paper presents a simple but accurate semi-empirical model especially focused on 65 nm MOST (MOS transistor) technologies and radio-frequency (RF) applications. It is obtained by means of simple dc and noise simulations extracted over a constrained set of MOSTs. The fundamental variable of the model is the MOST transconductance to current drain ratio gm/ID. Specifically it comprises the large signal DC normalized current, all conductances and transconductances and the normalized intrinsic capacitances. As well, noise MOST characteristics of flicker noise, white noise and MOST corner frequency description are provided. To validate the referred model the widely utilized cascoded common source low noise amplifier (CS-LNA), in 2.5 GHz and 5.3 GHz RF applications is picked. For the presented set of designs different gm/ID ratios are considered. Finally, the computed results are assessed by comparing with the outcomes of electrical simulations.Ministerio de Economía y Competitividad TEC2011-28302ElsevierMinisterio de Economía y Competitividad (MINECO). España2016info:eu-repo/semantics/articleinfo:eu-repo/semantics/acceptedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/74308https://doi.org/10.1016/j.vlsi.2015.07.018reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésIntegration: The VLSI Journal, 52, 228-236.TEC2011-28302http://dx.doi.org/10.1016/j.vlsi.2015.07.018info:eu-repo/semantics/openAccessoai:idus.us.es:11441/743082026-06-17T12:51:07Z
dc.title.none.fl_str_mv Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation
title Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation
spellingShingle Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation
Fiorelli, Rafaella
MOS transistor
gm/ID
Semi-empirical
RF
Nanometer technology
65 nm CMOS
Inversion level
CS-LNA
title_short Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation
title_full Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation
title_fullStr Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation
title_full_unstemmed Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation
title_sort Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation
dc.creator.none.fl_str_mv Fiorelli, Rafaella
Peralías Macías, Eduardo
author Fiorelli, Rafaella
author_facet Fiorelli, Rafaella
Peralías Macías, Eduardo
author_role author
author2 Peralías Macías, Eduardo
author2_role author
dc.contributor.none.fl_str_mv Ministerio de Economía y Competitividad (MINECO). España
dc.subject.none.fl_str_mv MOS transistor
gm/ID
Semi-empirical
RF
Nanometer technology
65 nm CMOS
Inversion level
CS-LNA
topic MOS transistor
gm/ID
Semi-empirical
RF
Nanometer technology
65 nm CMOS
Inversion level
CS-LNA
description This paper presents a simple but accurate semi-empirical model especially focused on 65 nm MOST (MOS transistor) technologies and radio-frequency (RF) applications. It is obtained by means of simple dc and noise simulations extracted over a constrained set of MOSTs. The fundamental variable of the model is the MOST transconductance to current drain ratio gm/ID. Specifically it comprises the large signal DC normalized current, all conductances and transconductances and the normalized intrinsic capacitances. As well, noise MOST characteristics of flicker noise, white noise and MOST corner frequency description are provided. To validate the referred model the widely utilized cascoded common source low noise amplifier (CS-LNA), in 2.5 GHz and 5.3 GHz RF applications is picked. For the presented set of designs different gm/ID ratios are considered. Finally, the computed results are assessed by comparing with the outcomes of electrical simulations.
publishDate 2016
dc.date.none.fl_str_mv 2016
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/acceptedVersion
format article
status_str acceptedVersion
dc.identifier.none.fl_str_mv https://hdl.handle.net/11441/74308
https://doi.org/10.1016/j.vlsi.2015.07.018
url https://hdl.handle.net/11441/74308
https://doi.org/10.1016/j.vlsi.2015.07.018
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv Integration: The VLSI Journal, 52, 228-236.
TEC2011-28302
http://dx.doi.org/10.1016/j.vlsi.2015.07.018
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Elsevier
publisher.none.fl_str_mv Elsevier
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,301603

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