Area-optimal transistor folding for 1-D gridded cell design

The 1-D design style with gridded design rules is gaining ground for addressing the printability issues in subwavelength photolithography. One of the synthesis problems in cell generation is transistor folding, which consists of breaking large transistors into smaller ones (legs) that can be placed...

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Detalles Bibliográficos
Autor: Cortadella, Jordi|||0000-0001-8114-250X
Tipo de recurso: artículo
Fecha de publicación:2013
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/27265
Acceso en línea:https://hdl.handle.net/2117/27265
https://dx.doi.org/10.1109/TCAD.2013.2269680
Access Level:acceso abierto
Palabra clave:Transistors
Cell generation
Design for manufacturability
Linear programming
Transistor folding
Transistor sizing
Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors
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spelling Area-optimal transistor folding for 1-D gridded cell designCortadella, Jordi|||0000-0001-8114-250XTransistorsCell generationDesign for manufacturabilityLinear programmingTransistor foldingTransistor sizingTransistorsÀrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::TransistorsThe 1-D design style with gridded design rules is gaining ground for addressing the printability issues in subwavelength photolithography. One of the synthesis problems in cell generation is transistor folding, which consists of breaking large transistors into smaller ones (legs) that can be placed in the active area of the cell. In the 1-D style, diffusion sharing between differently sized transistors is not allowed, thus implying a significant area overhead when active areas with different sizes are required. This paper presents a new formulation of the transistor folding problem in the context of 1-D design style and a mathematical model that delivers area-optimal solutions. The mathematical model can be customized for different variants of the problem, considering flexible transistor sizes and multiple-height cells. An innovative feature of the method is that area optimality can be guaranteed without calculating the actual location of the transistors. The model can also be enhanced to deliver solutions with good routability properties.Peer Reviewed20132013-11-0120152015-04-13journal articlehttp://purl.org/coar/resource_type/c_6501AMhttp://purl.org/coar/version/c_ab4af688f83e57aainfo:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/2117/27265https://dx.doi.org/10.1109/TCAD.2013.2269680reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/272652026-05-27T15:37:01Z
dc.title.none.fl_str_mv Area-optimal transistor folding for 1-D gridded cell design
title Area-optimal transistor folding for 1-D gridded cell design
spellingShingle Area-optimal transistor folding for 1-D gridded cell design
Cortadella, Jordi|||0000-0001-8114-250X
Transistors
Cell generation
Design for manufacturability
Linear programming
Transistor folding
Transistor sizing
Transistors
Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors
title_short Area-optimal transistor folding for 1-D gridded cell design
title_full Area-optimal transistor folding for 1-D gridded cell design
title_fullStr Area-optimal transistor folding for 1-D gridded cell design
title_full_unstemmed Area-optimal transistor folding for 1-D gridded cell design
title_sort Area-optimal transistor folding for 1-D gridded cell design
dc.creator.none.fl_str_mv Cortadella, Jordi|||0000-0001-8114-250X
author Cortadella, Jordi|||0000-0001-8114-250X
author_facet Cortadella, Jordi|||0000-0001-8114-250X
author_role author
dc.subject.none.fl_str_mv Transistors
Cell generation
Design for manufacturability
Linear programming
Transistor folding
Transistor sizing
Transistors
Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors
topic Transistors
Cell generation
Design for manufacturability
Linear programming
Transistor folding
Transistor sizing
Transistors
Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors
description The 1-D design style with gridded design rules is gaining ground for addressing the printability issues in subwavelength photolithography. One of the synthesis problems in cell generation is transistor folding, which consists of breaking large transistors into smaller ones (legs) that can be placed in the active area of the cell. In the 1-D style, diffusion sharing between differently sized transistors is not allowed, thus implying a significant area overhead when active areas with different sizes are required. This paper presents a new formulation of the transistor folding problem in the context of 1-D design style and a mathematical model that delivers area-optimal solutions. The mathematical model can be customized for different variants of the problem, considering flexible transistor sizes and multiple-height cells. An innovative feature of the method is that area optimality can be guaranteed without calculating the actual location of the transistors. The model can also be enhanced to deliver solutions with good routability properties.
publishDate 2013
dc.date.none.fl_str_mv 2013
2013-11-01
2015
2015-04-13
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
AM
http://purl.org/coar/version/c_ab4af688f83e57aa
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/27265
https://dx.doi.org/10.1109/TCAD.2013.2269680
url https://hdl.handle.net/2117/27265
https://dx.doi.org/10.1109/TCAD.2013.2269680
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,301603

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