Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks

In this paper, we present a review of the work [1]. The fast settlement of Privacy and Secure operations in the Internet of Things (IoT) is appealing the selection of mechanisms to achieve a higher level of security at the minimum cost and with reasonable performances. In recent years, dozens of pro...

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Autores: Tena Sánchez, Erica, Potestad Ordóñez, Francisco Eugenio, Zúñiga González, Virginia, Fernández García, Carlos, Mora Gutiérrez, José Miguel, Jiménez Fernández, Carlos Jesús, Acosta Jiménez, Antonio José
Tipo de documento: capítulo de livro
Estado:Versão publicada
Data de publicação:2022
País:España
Recursos:Universidad de Sevilla (US)
Repositório:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/161172
Acesso em linha:https://hdl.handle.net/11441/161172
Access Level:Acceso aberto
Palavra-chave:Hardware countermeasures
Gate level
VLSI design of cryptographic circuits
Side-channel attacks (SCAs)
Information security
Logic design
Internet of things (IoT)
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spelling Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis AttacksTena Sánchez, EricaPotestad Ordóñez, Francisco EugenioZúñiga González, VirginiaFernández García, CarlosMora Gutiérrez, José MiguelJiménez Fernández, Carlos JesúsAcosta Jiménez, Antonio JoséHardware countermeasuresGate levelVLSI design of cryptographic circuitsSide-channel attacks (SCAs)Information securityLogic designInternet of things (IoT)In this paper, we present a review of the work [1]. The fast settlement of Privacy and Secure operations in the Internet of Things (IoT) is appealing the selection of mechanisms to achieve a higher level of security at the minimum cost and with reasonable performances. In recent years, dozens of proposals have been presented to design circuits resistant to Power Analysis attacks. In this paper a deep review of the state of the art of gate-level countermeasures against Power Analysis attacks has been done, performing a comparison between hiding approaches (the power consumption is intended to be the same for all the data processed) and the ones considering a masking procedure (the data are masked and behave as random). The most relevant proposals in the literature, 35 for hiding and 6 for masking, have been analyzed, not only by using data provided by proposers, but also those included in other references for comparison.Fundación Tecnalia Research and InnovationTecnología ElectrónicaTIC180: Diseño de Circuitos Integrados Digitales y MixtosUniversidad de SevillaJunta de AndalucíaEuropean Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER)European Union (UE). H2020Ministerio de Ciencia e Innovación (MICIN). España2022info:eu-repo/semantics/bookPartinfo:eu-repo/semantics/publishedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/161172reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésInvestigación en Ciberseguridad. Actas de las VII Jornadas NacionalesSCAROT 1380823EU H2020 952622PID2020-116664RB-I00https://2022.jnic.es/info:eu-repo/semantics/openAccessoai:idus.us.es:11441/1611722026-06-17T12:51:07Z
dc.title.none.fl_str_mv Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks
title Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks
spellingShingle Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks
Tena Sánchez, Erica
Hardware countermeasures
Gate level
VLSI design of cryptographic circuits
Side-channel attacks (SCAs)
Information security
Logic design
Internet of things (IoT)
title_short Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks
title_full Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks
title_fullStr Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks
title_full_unstemmed Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks
title_sort Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks
dc.creator.none.fl_str_mv Tena Sánchez, Erica
Potestad Ordóñez, Francisco Eugenio
Zúñiga González, Virginia
Fernández García, Carlos
Mora Gutiérrez, José Miguel
Jiménez Fernández, Carlos Jesús
Acosta Jiménez, Antonio José
author Tena Sánchez, Erica
author_facet Tena Sánchez, Erica
Potestad Ordóñez, Francisco Eugenio
Zúñiga González, Virginia
Fernández García, Carlos
Mora Gutiérrez, José Miguel
Jiménez Fernández, Carlos Jesús
Acosta Jiménez, Antonio José
author_role author
author2 Potestad Ordóñez, Francisco Eugenio
Zúñiga González, Virginia
Fernández García, Carlos
Mora Gutiérrez, José Miguel
Jiménez Fernández, Carlos Jesús
Acosta Jiménez, Antonio José
author2_role author
author
author
author
author
author
dc.contributor.none.fl_str_mv Tecnología Electrónica
TIC180: Diseño de Circuitos Integrados Digitales y Mixtos
Universidad de Sevilla
Junta de Andalucía
European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER)
European Union (UE). H2020
Ministerio de Ciencia e Innovación (MICIN). España
dc.subject.none.fl_str_mv Hardware countermeasures
Gate level
VLSI design of cryptographic circuits
Side-channel attacks (SCAs)
Information security
Logic design
Internet of things (IoT)
topic Hardware countermeasures
Gate level
VLSI design of cryptographic circuits
Side-channel attacks (SCAs)
Information security
Logic design
Internet of things (IoT)
description In this paper, we present a review of the work [1]. The fast settlement of Privacy and Secure operations in the Internet of Things (IoT) is appealing the selection of mechanisms to achieve a higher level of security at the minimum cost and with reasonable performances. In recent years, dozens of proposals have been presented to design circuits resistant to Power Analysis attacks. In this paper a deep review of the state of the art of gate-level countermeasures against Power Analysis attacks has been done, performing a comparison between hiding approaches (the power consumption is intended to be the same for all the data processed) and the ones considering a masking procedure (the data are masked and behave as random). The most relevant proposals in the literature, 35 for hiding and 6 for masking, have been analyzed, not only by using data provided by proposers, but also those included in other references for comparison.
publishDate 2022
dc.date.none.fl_str_mv 2022
dc.type.none.fl_str_mv info:eu-repo/semantics/bookPart
info:eu-repo/semantics/publishedVersion
format bookPart
status_str publishedVersion
dc.identifier.none.fl_str_mv https://hdl.handle.net/11441/161172
url https://hdl.handle.net/11441/161172
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv Investigación en Ciberseguridad. Actas de las VII Jornadas Nacionales
SCAROT 1380823
EU H2020 952622
PID2020-116664RB-I00
https://2022.jnic.es/
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Fundación Tecnalia Research and Innovation
publisher.none.fl_str_mv Fundación Tecnalia Research and Innovation
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15.812429

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