Integration of a vector processing unit in a dual-issue out-of-order RISC-V processor

RISC-V continues to grow in popularity both in academia and industry. Recently, version 1.0 of the vector extension was ratified for public use and sparked renewed interest in vector processing. This is especially true in domains like High-Performance Computing (HPC) where the benefits of vectors ca...

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Detalhes bibliográficos
Autor: Rodas Quiroga, Narcís
Formato: tesis de maestría
Fecha de publicación:2024
País:España
Recursos:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/420746
Acesso em linha:https://hdl.handle.net/2117/420746
Access Level:acceso abierto
Palavra-chave:RISC microprocessors
Vector processing (Computer science)
Integrated circuits
RISC-V
Vector processing
OVI
RTL design
Address Generation Unit
ASIC Synthesis.
RISC (Microprocessadors)
Tractament vectorial
Circuits integrats
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Processadors digitals
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spelling Integration of a vector processing unit in a dual-issue out-of-order RISC-V processorRodas Quiroga, NarcísRISC microprocessorsVector processing (Computer science)Integrated circuitsRISC-VVector processingOVIRTL designAddress Generation UnitASIC Synthesis.RISC (Microprocessadors)Tractament vectorialCircuits integratsÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Processadors digitalsRISC-V continues to grow in popularity both in academia and industry. Recently, version 1.0 of the vector extension was ratified for public use and sparked renewed interest in vector processing. This is especially true in domains like High-Performance Computing (HPC) where the benefits of vectors can be fully exploited. This Master Thesis shows the integration of the Vitruvius Vector Processing Unit (VPU) with the Lagarto Ka, a dual-issue out-of-order RISC-V processor, through the Open Vector Interface (OVI). It describes the changes that have been made in the core to support the execution of vector instructions. The design has been tested, evaluated and compared to DVINO, a chip with earlier generations of the core and VPU. Lagarto Ka plus Vitruvius achieves up to 10 times more performance in vector instructions compared to its predecessor. It also reached a frequency of 1.5GHz when synthesized in 7nm.Universitat Politècnica de CatalunyaMoll Echeto, Francisco de BorjaMoretó Planas, Miquel20242024-02-0520242024-12-16master thesishttp://purl.org/coar/resource_type/c_bdccNAhttp://purl.org/coar/version/c_be7fb7dd8ff6fe43info:eu-repo/semantics/masterThesisapplication/pdfhttps://hdl.handle.net/2117/420746reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/4207462026-05-27T15:37:01Z
dc.title.none.fl_str_mv Integration of a vector processing unit in a dual-issue out-of-order RISC-V processor
title Integration of a vector processing unit in a dual-issue out-of-order RISC-V processor
spellingShingle Integration of a vector processing unit in a dual-issue out-of-order RISC-V processor
Rodas Quiroga, Narcís
RISC microprocessors
Vector processing (Computer science)
Integrated circuits
RISC-V
Vector processing
OVI
RTL design
Address Generation Unit
ASIC Synthesis.
RISC (Microprocessadors)
Tractament vectorial
Circuits integrats
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Processadors digitals
title_short Integration of a vector processing unit in a dual-issue out-of-order RISC-V processor
title_full Integration of a vector processing unit in a dual-issue out-of-order RISC-V processor
title_fullStr Integration of a vector processing unit in a dual-issue out-of-order RISC-V processor
title_full_unstemmed Integration of a vector processing unit in a dual-issue out-of-order RISC-V processor
title_sort Integration of a vector processing unit in a dual-issue out-of-order RISC-V processor
dc.creator.none.fl_str_mv Rodas Quiroga, Narcís
author Rodas Quiroga, Narcís
author_facet Rodas Quiroga, Narcís
author_role author
dc.contributor.none.fl_str_mv Moll Echeto, Francisco de Borja
Moretó Planas, Miquel
dc.subject.none.fl_str_mv RISC microprocessors
Vector processing (Computer science)
Integrated circuits
RISC-V
Vector processing
OVI
RTL design
Address Generation Unit
ASIC Synthesis.
RISC (Microprocessadors)
Tractament vectorial
Circuits integrats
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Processadors digitals
topic RISC microprocessors
Vector processing (Computer science)
Integrated circuits
RISC-V
Vector processing
OVI
RTL design
Address Generation Unit
ASIC Synthesis.
RISC (Microprocessadors)
Tractament vectorial
Circuits integrats
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Processadors digitals
description RISC-V continues to grow in popularity both in academia and industry. Recently, version 1.0 of the vector extension was ratified for public use and sparked renewed interest in vector processing. This is especially true in domains like High-Performance Computing (HPC) where the benefits of vectors can be fully exploited. This Master Thesis shows the integration of the Vitruvius Vector Processing Unit (VPU) with the Lagarto Ka, a dual-issue out-of-order RISC-V processor, through the Open Vector Interface (OVI). It describes the changes that have been made in the core to support the execution of vector instructions. The design has been tested, evaluated and compared to DVINO, a chip with earlier generations of the core and VPU. Lagarto Ka plus Vitruvius achieves up to 10 times more performance in vector instructions compared to its predecessor. It also reached a frequency of 1.5GHz when synthesized in 7nm.
publishDate 2024
dc.date.none.fl_str_mv 2024
2024-02-05
2024
2024-12-16
dc.type.none.fl_str_mv master thesis
http://purl.org/coar/resource_type/c_bdcc
NA
http://purl.org/coar/version/c_be7fb7dd8ff6fe43
dc.type.openaire.fl_str_mv info:eu-repo/semantics/masterThesis
format masterThesis
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/420746
url https://hdl.handle.net/2117/420746
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Universitat Politècnica de Catalunya
publisher.none.fl_str_mv Universitat Politècnica de Catalunya
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,811543

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