Implementation of a DDR3 PHY in a 22nm technology
One of the bottlenecks in the performance of academic RISC-V ASIC processors is high-speed memory access. The use of high-speed DDR RAM chips on the board requires the integration in the ASIC of a very complex physical interface block (PHY) that encompasses analog and digital parts. This PHY block i...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2024 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/422303 |
| Acceso en línea: | https://hdl.handle.net/2117/422303 |
| Access Level: | acceso abierto |
| Palabra clave: | Application specific integrated circuits--Design and construction RISC microprocessors DDR3 PHY phyisical implementation ASIC Circuits integrats d'aplicació específica--Disseny i construcció Microprocessadors RISC Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
| Sumario: | One of the bottlenecks in the performance of academic RISC-V ASIC processors is high-speed memory access. The use of high-speed DDR RAM chips on the board requires the integration in the ASIC of a very complex physical interface block (PHY) that encompasses analog and digital parts. This PHY block is thus technology-specific and very expensive to acquire. This master's thesis will start from a DDR3 PHY design verified on FPGA with the goal to obtain a physical implementation in ASIC 22nm technology. This implies the design of selected blocks in full custom as well as the synthesis and place and route phases of the top-level design to obtain a realistic layout. |
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