SoC hardware platform for Multi-core RISC-V processors based on OpenSource libraries
This thesis, developed at Openchip, presents the design of a configurable SoC prototyping platform for RISC-V processors using open-source frameworks. The platform was designed to enable rapid prototyping, support flexible configurations, and allow evaluation of Performance, Power, and Area (PPA) ac...
| Autor: | |
|---|---|
| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2025 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/452534 |
| Acceso en línea: | https://hdl.handle.net/2117/452534 |
| Access Level: | acceso abierto |
| Palabra clave: | RISC microprocessors Open source software Array processors Hardware Architecture SoC Microprocessadors RISC Programari lliure Processadors vectorials Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica |
| Sumario: | This thesis, developed at Openchip, presents the design of a configurable SoC prototyping platform for RISC-V processors using open-source frameworks. The platform was designed to enable rapid prototyping, support flexible configurations, and allow evaluation of Performance, Power, and Area (PPA) across design points. The project followed three stages: exploration of open-source hardware libraries, SoC platform development, and performance analysis. Benchmarking with scalar and vector processors showed results consistent with theoretical expectations. In particular, longer vectors achieved near-maximum performance and improved resilience to memory latency, while shorter vectors suffered from underutilization. These results validate the platform as an effective platform for processor evaluation, with future extensions including power and area analysis, larger workloads, and multi-core experiments. |
|---|