Integration of a vector processing unit in a dual-issue out-of-order RISC-V processor

RISC-V continues to grow in popularity both in academia and industry. Recently, version 1.0 of the vector extension was ratified for public use and sparked renewed interest in vector processing. This is especially true in domains like High-Performance Computing (HPC) where the benefits of vectors ca...

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Detalles Bibliográficos
Autor: Rodas Quiroga, Narcís
Tipo de recurso: tesis de maestría
Fecha de publicación:2024
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/420746
Acceso en línea:https://hdl.handle.net/2117/420746
Access Level:acceso abierto
Palabra clave:RISC microprocessors
Vector processing (Computer science)
Integrated circuits
RISC-V
Vector processing
OVI
RTL design
Address Generation Unit
ASIC Synthesis.
RISC (Microprocessadors)
Tractament vectorial
Circuits integrats
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Processadors digitals
Descripción
Sumario:RISC-V continues to grow in popularity both in academia and industry. Recently, version 1.0 of the vector extension was ratified for public use and sparked renewed interest in vector processing. This is especially true in domains like High-Performance Computing (HPC) where the benefits of vectors can be fully exploited. This Master Thesis shows the integration of the Vitruvius Vector Processing Unit (VPU) with the Lagarto Ka, a dual-issue out-of-order RISC-V processor, through the Open Vector Interface (OVI). It describes the changes that have been made in the core to support the execution of vector instructions. The design has been tested, evaluated and compared to DVINO, a chip with earlier generations of the core and VPU. Lagarto Ka plus Vitruvius achieves up to 10 times more performance in vector instructions compared to its predecessor. It also reached a frequency of 1.5GHz when synthesized in 7nm.