Design of a RISC-V Core Developed in SystemVerilog
This thesis presents the development of a custom RISC-V processor, designed and implemented as part of an educational project focused on computer architecture and hardware design. The processor supports the standard RV32IM instruction set and includes custom instructions to interact with external pe...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2025 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/452658 |
| Acceso en línea: | https://hdl.handle.net/2117/452658 |
| Access Level: | acceso abierto |
| Palabra clave: | RISC microprocessors RISC-V Microprocessadors RISC Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica |
| Sumario: | This thesis presents the development of a custom RISC-V processor, designed and implemented as part of an educational project focused on computer architecture and hardware design. The processor supports the standard RV32IM instruction set and includes custom instructions to interact with external peripherals through GPIO interfaces. The design follows a five-stage pipeline architecture and has been developed using SystemVerilog as hardware description language. The validation process included both simulation using Verilator and physical implementation on an FPGA board. |
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