Sincronización de sistemas electrónicos en un mismo circuito integrado: Synchronization of Integrated Systems on a Chip

In the present paper, the non-conventional interconnected and coupled ring oscillators approach working as clock distribution networks to synchronize electronic systems on a chip (SoC) is proposed. Typical CMOS (Complementary Metal-Oxide Semiconductor) N-well 0.35 μm Austria Micro Systems process pa...

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Detalles Bibliográficos
Autores: MONICO LINARES ARANDA, OSCAR GONZÁLEZ DÍAZ
Tipo de recurso: artículo
Estado:Versión aceptada para publicación
Fecha de publicación:2012
País:México
Institución:Instituto Nacional de Astrofísica, Óptica y Electrónica
Repositorio:Repositorio Institucional del INAOE
Idioma:español
OAI Identifier:oai:inaoe.repositorioinstitucional.mx:1009/2050
Acceso en línea:http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2050
Access Level:acceso abierto
Palabra clave:info:eu-repo/classification/Redes de reloj/Clock networks
info:eu-repo/classification/Sincronización/Synchronization
info:eu-repo/classification/Sistemas en un chip/Systems on a chip
info:eu-repo/classification/Circuitos digitales/Digital circuits
info:eu-repo/classification/Osciladores controlados por voltaje/Voltage controlled oscillators
info:eu-repo/classification/cti/1
info:eu-repo/classification/cti/22
info:eu-repo/classification/cti/2203
info:eu-repo/classification/cti/220307
Descripción
Sumario:In the present paper, the non-conventional interconnected and coupled ring oscillators approach working as clock distribution networks to synchronize electronic systems on a chip (SoC) is proposed. Typical CMOS (Complementary Metal-Oxide Semiconductor) N-well 0.35 μm Austria Micro Systems process parameters were used for conventional and non-conventional clock distribution nets design and simulation. Experimental results from local and global clock distribution networks fabricated using a CMOS 0.35 μm process show that the use of interconnected rings arrays, as globally asynchronous locally synchronous (GALS) clock distribution networks, represent an appropriate approach due to good performance regarding scalability, low clock-skew, high-speed, faults tolerant and robust under process variations, regularity, and modularity.