Diseño de un circuito integrado de pruebas para tecnología CMOS 0.8 micras
The manufacture of integrated circuits requires several quality standards that allow the correct functioning of the final devices. These quality standards are closely related to the characteristics of the manufacturing process; Therefore, it's important to verify that all stages of the manufact...
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| Tipo de recurso: | tesis de maestría |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2019 |
| País: | México |
| Institución: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Repositorio Institucional del INAOE |
| Idioma: | español |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/2020 |
| Acceso en línea: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2020 |
| Access Level: | acceso abierto |
| Palabra clave: | info:eu-repo/classification/Inspec/Chip de pruebas info:eu-repo/classification/Inspec/0.8 Micrometros info:eu-repo/classification/Inspec/Tecnología CMOS info:eu-repo/classification/Inspec/LATCHUP info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 info:eu-repo/classification/cti/220307 |
| Sumario: | The manufacture of integrated circuits requires several quality standards that allow the correct functioning of the final devices. These quality standards are closely related to the characteristics of the manufacturing process; Therefore, it's important to verify that all stages of the manufacturing process were successful. The importance of this verification increased with the mass manufacturing of integrated circuits. In order to detect and reduce the problems of failures in the manufacture of integrated circuits, the concept of integrated test circuit was developed. This integrated circuit contains all the test structures necessary to characterize important stages of the manufacturing process. When a laboratory or a factory develops a new technology or starts the production of ICs with a certain technology, it is necessary to design a new integrated test circuit. The objective of this work is to design a complete set of devices and structures that allow testing (mainly electrical) the process. In this thesis, an integrated test circuit is designed for a CMOS technology of 0.8 μm, with a total of 76 structures spread over 60 modules of pads; The final CIP has dimensions of 0.885 cm x 0.97115 cm. L-Edit software is used to design the geometric pattern. |
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