Optimization of CMOS OTAs applying metaheuristics
Analog integrated circuits design has been a challenge, due to the large number of parameters, design variables and trade-offs among the electrical characteristics of each circuit. Therefore, different optimization techniques have been implemented for the design of ICs. One of the most used techniqu...
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| Tipo de recurso: | tesis de maestría |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2019 |
| País: | México |
| Institución: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Repositorio Institucional del INAOE |
| Idioma: | inglés |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/1792 |
| Acceso en línea: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1792 |
| Access Level: | acceso abierto |
| Palabra clave: | info:eu-repo/classification/Inspec/Metaheuristics info:eu-repo/classification/Inspec/Design info:eu-repo/classification/Inspec/Optimization info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 |
| Sumario: | Analog integrated circuits design has been a challenge, due to the large number of parameters, design variables and trade-offs among the electrical characteristics of each circuit. Therefore, different optimization techniques have been implemented for the design of ICs. One of the most used techniques is the application of metaheuristics for the sizing of ICs, since they provide a set of feasible solutions according to the parameter to be optimized. In this Thesis mono and multi-objective metaheuristics are applied for the sizing of Transconductance Operational Amplifiers (OTAs) with the aim of minimizing the silicon area and guaranteeing that the MOS transistors operate within a suitable direct current operating point (DCOP). In this Thesis are described population-based optimization algorithms and evolutionary algorithms, such as Particle Swarm Optimization (PSO), Many Optimization Liaisons (MOL) and Non-dominated Sorting Genetic Algorithm-II (NSGA-II) applied to the sizing of both the Miller and Recycled Folded Cascode OTAs, using UMC 180nm and onsemiconductor 500nm technologies, respectively. Moreover, the design and characterization of a Miller OTA is performed using the quadratic model. Subsequently, the procedure that was carried out to estimate the silicon area of each OTA and the conditions to ensure that MOS transistors operate within the strong inversion region is described. The behaviors and results of the PSO and MOL particles through the generations and the Pareto fronts corresponding to the NSGA-II algorithm are shown. Finally, according to the results obtained with the algorithms for the sizing of the OTAs, the layout and the post-layout simulations are carried out to verify that the optimized circuits are robust to process, voltage and temperature variations (PVT). |
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