CCO and VCO implemented by CMOS current mode logic stages
This thesis focuses in the design and implementation of voltage controlled oscillators (VCO) and current controlled oscillators (CCO) connected in a ring structure and based in current mode logic (CML) stages. The target frequency of oscillation of these ring oscillators (RO) is around the GHz order...
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| Tipo de recurso: | tesis de maestría |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2019 |
| País: | México |
| Institución: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Repositorio Institucional del INAOE |
| Idioma: | inglés |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/1791 |
| Acceso en línea: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1791 |
| Access Level: | acceso abierto |
| Palabra clave: | info:eu-repo/classification/Inspec/CML info:eu-repo/classification/Inspec/Buffer info:eu-repo/classification/Inspec/VCO info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 |
| Sumario: | This thesis focuses in the design and implementation of voltage controlled oscillators (VCO) and current controlled oscillators (CCO) connected in a ring structure and based in current mode logic (CML) stages. The target frequency of oscillation of these ring oscillators (RO) is around the GHz order and must be tunable within a wide range of voltage or current, according to the case. In order to design both a VCO and a CCO, a basic CML delay cell with passive load is designed and characterized for different load values, so as to determine how circuit parameter variations affect the frequency response. This CML buffer design is extended to a CML-based latch. The transition needed to be able to control the oscillation frequency of a RO is accomplished through the replacement of the passive load in the CML delay cell with an active load whose value is determined by the control voltaje magnitude. The CML based VCO’s delay cell is characterized in the DC, AC and time domains and simulated under process, voltage and temperature (PVT) variations analogously to the CML delay cell with passive load. These characterizations, allow to design and implement a CML based CCO, by fixing the control voltage in the value that allows the widest control current range. A CMOS based RO is also implemented and characterized to be able to compare the performance of both logics. Analytical expressions are derived to approach the frequency behavior of the CML buffers that can be used to verify tolerances of the circuit parameters. All of the designs, both of the CML based buffers, CMOS based buffer and CML based latches are simulated under different load values and within ranges of values published in the literature. Finally, a layout is implemented of the VCO’s delay cell and of the VCO and postlayout simulations are performed to verify the circuit’s performance. |
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