Study and comparison of CMOS layouts for applications in analog circuits
This study presents different layouts techniques (serpentine, concentric, interdigitated) applied to a differential amplifier designed in commercial technology CMOS (0.6 μm). It was observed that serpentine technique improves by 6 to 7 electrical parameters, where area was reduced (64%) and power co...
| Autores: | , |
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| Tipo de recurso: | artículo |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2012 |
| País: | México |
| Institución: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Repositorio Institucional del INAOE |
| Idioma: | inglés |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/2124 |
| Acceso en línea: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2124 |
| Access Level: | acceso abierto |
| Palabra clave: | info:eu-repo/classification/Inspec/Integrated circuit (IC) info:eu-repo/classification/Inspec/Layout info:eu-repo/classification/Inspec/Operational amplifier info:eu-repo/classification/Inspec/Serpentine info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 |
| Sumario: | This study presents different layouts techniques (serpentine, concentric, interdigitated) applied to a differential amplifier designed in commercial technology CMOS (0.6 μm). It was observed that serpentine technique improves by 6 to 7 electrical parameters, where area was reduced (64%) and power consumption diminishes until a 57% with respect to conventional technique. Thus designer can optimally use different abstraction levels during integrated circuits (IC) design, by applying the best layout technique towards efficient systems. |
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