Robust to PVT, high DC gain amplifier for CT ΣΔ modulators on SOI CMOS technology
SOI technology is particularly good for low voltage, low power and high speed digital systems because it has reduced drain to substrate capacitance due to the inclusion of an insulator layer between substrate and active region. Nonetheless, SOI is a pure digital technology making the analog design a...
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| Formato: | tesis de maestría |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2011 |
| País: | México |
| Recursos: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Repositorio Institucional del INAOE |
| Idioma: | inglés |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/684 |
| Acesso em linha: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/684 |
| Access Level: | acceso abierto |
| Palavra-chave: | info:eu-repo/classification/Modulación Sigma-delta/Sigma-delta modulation info:eu-repo/classification/Amplificadores operacionales/Operational amplifiers info:eu-repo/classification/Silicio en aislador/Silicon-on-insulator info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 |
| Resumo: | SOI technology is particularly good for low voltage, low power and high speed digital systems because it has reduced drain to substrate capacitance due to the inclusion of an insulator layer between substrate and active region. Nonetheless, SOI is a pure digital technology making the analog design a challenging task. This work presents the design of a relatively high DC gain amplifier on SOI technology, which must be robust to PVT variations. In order to evaluate the performance of amplifier, it is used in a continuous time sigma delta modulator. Two OTAs was proposed in this work. As a first consideration, self-cascode transistor was used to improve the output impedance and reduce the influence of voltage supply in the amplifier gain. Also, a current shunt technique was applied to first proposed amplifier to enhance DC gain. However, the PVT variations considerably affects the performance of amplifier, so a second proposal was accomplished. Sums of transconductance was used together self-cascode transistor to reduce sensitivity to PVT variations. The last proposed amplifier achieves a DC gain of 53 dB with GBW=575 MHz and a power consumption of 1.25 mW. Simulation results shows that the amplifier has a DC gain over 50 dB despite PVT variations. To drive resistive load of the first integrator of the modulator, different buffer was proposed in order to have wide input and output voltage excursion and low output impedance. Final Buffer implementation is a feedback amplifier which has complementary input differential pairs and a class AB output stage. Open loop gain of the amplifier is 57 dB while has close loop output impedance of 55 Ω Buffer’s harmonic distortion is around 0.1 % for all PVT variations with a voltage excursion of 600 mV. A comparison between two-stage Miller amplifier and proposed amplifier was done to see how PVT variations affect the performance of a commonly used amplifier. Finally, both amplifiers are included in the modulator to validate the robustness of the proposed amplifier. Simulations of the whole modulator show that the SNDR of modulator is improved over 9 dB using the proposed amplifier. The design was done on SOI 45 nm IBM technology and simulations were carried out in Hspice. |
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