PVT compensated PLL in 45nm SOI-CMOS technology
In this work the design of a compensated to process, voltage and temperature |PVT| PLL is presented, which is based in a ring oscillator. The circuit is designed in a nanometer technology, in the 45nm IBM SOI-CMOS process specifically. At first, the impact of PVT variations on the performance of an...
| Autor: | |
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| Tipo de recurso: | tesis de maestría |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2012 |
| País: | México |
| Institución: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Repositorio Institucional del INAOE |
| Idioma: | inglés |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/735 |
| Acceso en línea: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/735 |
| Access Level: | acceso abierto |
| Palabra clave: | info:eu-repo/classification/Phase locked loops/Phase locked loops info:eu-repo/classification/PVT/PVT compensation info:eu-repo/classification/Oscilador de anillo/Ring oscillator info:eu-repo/classification/Silicon/Silicon on insulator info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 |
| Sumario: | In this work the design of a compensated to process, voltage and temperature |PVT| PLL is presented, which is based in a ring oscillator. The circuit is designed in a nanometer technology, in the 45nm IBM SOI-CMOS process specifically. At first, the impact of PVT variations on the performance of an analog circuit is presented; also, a description of the used technology as well as its disadvantages in the design of analog circuits are made. The behavior of a PLL and the inuence of PVT variations on its performance are described; the sensitivity of performance metric like bandwidth and settling time is presented. In addition, the behavior of all the components that form a PLL is studied, highlighting them variability to PVT. Then, the design of each one of them is made, making emphasis in some design considerations that increase the robustness of the circuit. The states-machine topology for the phase detector is selected because of high excursion range. For the charge pump, the use of an amplifier at its output is proposed, with the aim to reduce its dynamic range; this decrease the mismatch between the UP and DOWN currents due to the channel modulation effect. For the ring oscillator a pseudo-differential current controlled topology is selected, in order to guarantee the symmetry of the oscillation waveform and to reduce the variability of the tuning gain. Moreover, a compensation network is proposed, which adjust the bias current based on the process condition and temperature. With this network a reduction of the variability of the free-running frequency to 2.9% over 7.2GHz is achieved. Furthermore, the impact of history-effect of a SOI transistors over the settling of the frequency of a ring oscillator is presented. Finally, all the PLL is implemented and its performance is verified by the estimation of the frequency response through the characterization of the transient response. As a result, a PLL with a reduced variability of its bandwidth is achieved, whose power consumption is 5.4mW and jitter of 1.6ps RMS. |
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