ADC tipo folding en modo corriente a 10 bits 1 GM/s basado en celdas winner take all
Unrelenting growth in digital comunications, multimedia and others consumers products in recent years has traslated into incrasing demands for Analog to Digital Converters (ADCs) of 8-10 bits resolutions and sample rates in excess of 100 MHz. This work shows a 10 bits 1GS/s current mode Folding ADC...
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| Tipo de recurso: | tesis de maestría |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2018 |
| País: | México |
| Institución: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Repositorio Institucional del INAOE |
| Idioma: | español |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/1724 |
| Acceso en línea: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1724 |
| Access Level: | acceso abierto |
| Palabra clave: | info:eu-repo/classification/Inspec/Analog-to-digital converter info:eu-repo/classification/Inspec/Winner take all info:eu-repo/classification/Inspec/Design rule checker info:eu-repo/classification/Inspec/Layout vs schematic info:eu-repo/classification/Inspec/Effective number of bits info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 info:eu-repo/classification/cti/330703 |
| Sumario: | Unrelenting growth in digital comunications, multimedia and others consumers products in recent years has traslated into incrasing demands for Analog to Digital Converters (ADCs) of 8-10 bits resolutions and sample rates in excess of 100 MHz. This work shows a 10 bits 1GS/s current mode Folding ADC design in transistor level. This approach is due to voltage mode issues as limited riel supply and the high power consumption in high resolutions (10 bits). The ADC quantizer is based in Winner Take All and comparators and interpolated stage is not required in the present work as do the voltaje mode ADCs. The statics (DNL & INL), and the dynamics characterizations (SNR & ENOB) was done as well as layout development was made using CADENCE Virtuoso, DRC, LVS and paraitic extractions was also perform. The design was fabricated in IMEC technology of 180nm. |
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