Estimación de parámetros de un motor de inducción usando redes neuronales y sistemas neurodifusos
This thesis presents the estimation of parameters of an induction motor using neural networks and neurofuzzy systems; such parameters are the rotor ux, the position of the rotor ux and the motor speed. These parameters are indispensable for a vector control scheme. The methodology is based on the se...
| Autor: | |
|---|---|
| Tipo de recurso: | tesis de maestría |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2018 |
| País: | México |
| Institución: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Repositorio Institucional del INAOE |
| Idioma: | español |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/2029 |
| Acceso en línea: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2029 |
| Access Level: | acceso abierto |
| Palabra clave: | info:eu-repo/classification/Inspec/Estimate info:eu-repo/classification/Inspec/Induction motor info:eu-repo/classification/Inspec/Parameters info:eu-repo/classification/Inspec/Neural network info:eu-repo/classification/Inspec/Vivado HLS info:eu-repo/classification/Inspec/ANFIS info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 |
| Sumario: | This thesis presents the estimation of parameters of an induction motor using neural networks and neurofuzzy systems; such parameters are the rotor ux, the position of the rotor ux and the motor speed. These parameters are indispensable for a vector control scheme. The methodology is based on the search of architectures that can estimate these parameters through the training of neural networks and neurofuzzy systems. The selection of the architectures is based on a heuristic reasoning, making tests and observing the behavior of the root mean square error. Once the architectures were obtained, they were described in High-Level Synthesis, using Vivado HLS, a tool of Xilinx. This description was accomplished in C++, where results of the use of hardware utilization and latency are presented, for a later implementation on a FPGA. The validation of the architectures was analyzed by System Generator, which allows the modeling in Simulink in order to explore the operation without the use of tracing the design to hardware. |
|---|