Arquitectura de un convertidor analógico digital de plegado basado en celdas winner take all
In recent years, the increase in digital applications requires digital analog converters (ADCs) with a high conversion rate, high resolution and low power consumption, for which many topologies have been proposed, among them the technique of folding, which reduces the number of comparators causing a...
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| Formato: | tesis de maestría |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2017 |
| País: | México |
| Recursos: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Repositorio Institucional del INAOE |
| Idioma: | español |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/2030 |
| Acesso em linha: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/2030 |
| Access Level: | acceso abierto |
| Palavra-chave: | info:eu-repo/classification/Inspec/Winner take all info:eu-repo/classification/Inspec/Analog digital converter info:eu-repo/classification/Inspec/Folding architecture. info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 info:eu-repo/classification/cti/330703 |
| Resumo: | In recent years, the increase in digital applications requires digital analog converters (ADCs) with a high conversion rate, high resolution and low power consumption, for which many topologies have been proposed, among them the technique of folding, which reduces the number of comparators causing a decrease in power consumption; despite its advantages, the number of bits that are resolved is not greater than 7. This work presents a new topology for a folding amplifier based on Winner-Take- All (WTA) cells, with input in current mode and outputs in current and voltage mode, and designed in CMOS technology. 0.18 mum. In this work, 3 WTA cells were implemented and compared, and based on their gain and power consumption one of them was chosen for the realization of the folding amplifier; the reference currents for the WTA's have compensation for the temperature and for the voltage outputs a circuit is proposed that reduces the effect of clockfeedthrough, generated by the switches. The folding amplifier was designed to achieve 32 foldings. Finally, a new topology of a folding ADC is presented using the folding amplifier based on WTA's, which has several advantages such as not using T&H and comparators, besides having outputs in current and voltage mode. A 10-bit resolution is proposed for the ADC; the system was simulated using HSPICE textsuperscript textregistered 2007 and the results obtained show a DNL = ±0,1 and INL = ±0,4, however, the ENOB = 7,0646 this bit loss, it must to the use of mirrors like entrance for the WTA, the degradation of the impedance of exit and the little robustness of the WTA |
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