Systems for fractional sampling rate conversion

This thesis treats the design of decimation filters for fractional sampling rate conversion system, applicable for Software Radio (SR). We first present a general introduction of Software Radio technology along with the brief description of radio system architecture, multirate techniques, and progra...

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Detalles Bibliográficos
Autor: NAINA RAO NAGRALE
Tipo de recurso: tesis de maestría
Estado:Versión aceptada para publicación
Fecha de publicación:2007
País:México
Institución:Instituto Nacional de Astrofísica, Óptica y Electrónica
Repositorio:Repositorio Institucional del INAOE
Idioma:inglés
OAI Identifier:oai:inaoe.repositorioinstitucional.mx:1009/645
Acceso en línea:http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/645
Access Level:acceso abierto
Palabra clave:info:eu-repo/classification/Radio de software/Software radio
info:eu-repo/classification/Chips de procesamiento de señales digitales/Digital signal processing chips
info:eu-repo/classification/Comunicación digital/Digital communication
info:eu-repo/classification/cti/1
info:eu-repo/classification/cti/22
info:eu-repo/classification/cti/2203
info:eu-repo/classification/cti/330706
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spelling Systems for fractional sampling rate conversionNAINA RAO NAGRALEinfo:eu-repo/classification/Radio de software/Software radioinfo:eu-repo/classification/Chips de procesamiento de señales digitales/Digital signal processing chipsinfo:eu-repo/classification/Comunicación digital/Digital communicationinfo:eu-repo/classification/cti/1info:eu-repo/classification/cti/22info:eu-repo/classification/cti/2203info:eu-repo/classification/cti/330706info:eu-repo/classification/cti/330706This thesis treats the design of decimation filters for fractional sampling rate conversion system, applicable for Software Radio (SR). We first present a general introduction of Software Radio technology along with the brief description of radio system architecture, multirate techniques, and programmable logic devices (PLDs). Then, the basic principles of Sampling Rate Conversion (SRC) is presented, including various methods for decimation and their impacts on the filter complexity. Further, a review of the Finite Impulse Response (FIR) filters has been done, along with the methods of rounding and sharpening for efficient filter design. The raising technique, block filtering and time varying polyphase structures are also revised. Overview of existing sampling rate conversion filters has been presented, which includes Cascaded Integrated Comb (CIC) filter, Polynomial filter and Time Varying CIC filter. Using multirate techniques and polyphase representation, a simple method of designing fractional sampling rate conversion system based on the Interpolated Finite Impulse Response (IFIR) filter has been proposed. Finally, the proposed algorithm is simulated in MATLAB and implemented in the SPARTAN 3 family of the Xilinx’s Field Programmable Gate Array (FPGA) using project navigator Xilinx ISE 8.2i. The input and output of the implemented structure is verified in Symphony EDA Sonata 3.1. All the proposed MATLAB functions and VHDL programs are included in Appendix.La Presente tesis trata el diseño de filtros de decimación para sistemas de conversión de la razón de muestreo fraccional utilizable en Software Radio. En principio se presenta una introducción general de la tecnología Software Radio incluyendo arquitectura, técnicas de multirazon y dispositivos lógicos programables. Posteriormente, se muestran los principios básicos de conversión de muestreo así como los métodos de decimación y su impacto en la complejidad de filtros. Además, se presenta una revisión de los filtros, FIR ( Respuesta al impulso Finita), incluyendo los métodos redondeo y afilado para el diseño eficiente de filtros, técnicas de elevación y métodos block filtering. Una vista general de filtros de razón de muestreo existentes es presentada, la cual contiene los filtros Cascaded Integrated Comb (CIC) Filtro, filtro Polynomial, and Time varying CIC Filter. Se propone un método simple de diseño de un sistema de conversión de la razón de muestreo fraccional basada en filtros Interpolated Finite Impulse Response (IFIR) usando técnicos multirazon y representación polifase. Finalmente, el algoritmo propuesta es simulado en MATLAB e implementado mediante SPARTAN 3 familia de Field Programmable Gate Array (FPGA) usando navegador Xilinx ISE 8.2i. La entrada y la salida de la estructura implementada es verificada en Symphony EDA Sonata 3.1. Todas las funciones MATLAB propuestas y las programas VHDL son incluidos en el Apéndice.Instituto Nacional de Astrofísica, Óptica y ElectrónicaGORDANA JOVANOVIC DOLECEKJorge Martinez_Carballido2007-07info:eu-repo/semantics/masterThesisinfo:eu-repo/semantics/acceptedVersionapplication/pdfhttp://inaoe.repositorioinstitucional.mx/jspui/handle/1009/645reponame:Repositorio Institucional del INAOEinstname:Instituto Nacional de Astrofísica, Óptica y Electrónicainstacron:INAOEengcitation:Rao Nagrale, Nainainfo:eu-repo/semantics/openAccesshttp://creativecommons.org/licenses/by-nc-nd/4.0oai:inaoe.repositorioinstitucional.mx:1009/6452024-08-28T03:22:46Z
dc.title.none.fl_str_mv Systems for fractional sampling rate conversion
title Systems for fractional sampling rate conversion
spellingShingle Systems for fractional sampling rate conversion
NAINA RAO NAGRALE
info:eu-repo/classification/Radio de software/Software radio
info:eu-repo/classification/Chips de procesamiento de señales digitales/Digital signal processing chips
info:eu-repo/classification/Comunicación digital/Digital communication
info:eu-repo/classification/cti/1
info:eu-repo/classification/cti/22
info:eu-repo/classification/cti/2203
info:eu-repo/classification/cti/330706
info:eu-repo/classification/cti/330706
title_short Systems for fractional sampling rate conversion
title_full Systems for fractional sampling rate conversion
title_fullStr Systems for fractional sampling rate conversion
title_full_unstemmed Systems for fractional sampling rate conversion
title_sort Systems for fractional sampling rate conversion
dc.creator.none.fl_str_mv NAINA RAO NAGRALE
author NAINA RAO NAGRALE
author_facet NAINA RAO NAGRALE
author_role author
dc.contributor.none.fl_str_mv GORDANA JOVANOVIC DOLECEK
Jorge Martinez_Carballido
dc.subject.none.fl_str_mv info:eu-repo/classification/Radio de software/Software radio
info:eu-repo/classification/Chips de procesamiento de señales digitales/Digital signal processing chips
info:eu-repo/classification/Comunicación digital/Digital communication
info:eu-repo/classification/cti/1
info:eu-repo/classification/cti/22
info:eu-repo/classification/cti/2203
info:eu-repo/classification/cti/330706
info:eu-repo/classification/cti/330706
topic info:eu-repo/classification/Radio de software/Software radio
info:eu-repo/classification/Chips de procesamiento de señales digitales/Digital signal processing chips
info:eu-repo/classification/Comunicación digital/Digital communication
info:eu-repo/classification/cti/1
info:eu-repo/classification/cti/22
info:eu-repo/classification/cti/2203
info:eu-repo/classification/cti/330706
info:eu-repo/classification/cti/330706
description This thesis treats the design of decimation filters for fractional sampling rate conversion system, applicable for Software Radio (SR). We first present a general introduction of Software Radio technology along with the brief description of radio system architecture, multirate techniques, and programmable logic devices (PLDs). Then, the basic principles of Sampling Rate Conversion (SRC) is presented, including various methods for decimation and their impacts on the filter complexity. Further, a review of the Finite Impulse Response (FIR) filters has been done, along with the methods of rounding and sharpening for efficient filter design. The raising technique, block filtering and time varying polyphase structures are also revised. Overview of existing sampling rate conversion filters has been presented, which includes Cascaded Integrated Comb (CIC) filter, Polynomial filter and Time Varying CIC filter. Using multirate techniques and polyphase representation, a simple method of designing fractional sampling rate conversion system based on the Interpolated Finite Impulse Response (IFIR) filter has been proposed. Finally, the proposed algorithm is simulated in MATLAB and implemented in the SPARTAN 3 family of the Xilinx’s Field Programmable Gate Array (FPGA) using project navigator Xilinx ISE 8.2i. The input and output of the implemented structure is verified in Symphony EDA Sonata 3.1. All the proposed MATLAB functions and VHDL programs are included in Appendix.
publishDate 2007
dc.date.none.fl_str_mv 2007-07
dc.type.none.fl_str_mv info:eu-repo/semantics/masterThesis
info:eu-repo/semantics/acceptedVersion
format masterThesis
status_str acceptedVersion
dc.identifier.none.fl_str_mv http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/645
url http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/645
dc.language.none.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv citation:Rao Nagrale, Naina
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
http://creativecommons.org/licenses/by-nc-nd/4.0
eu_rights_str_mv openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-nd/4.0
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Instituto Nacional de Astrofísica, Óptica y Electrónica
publisher.none.fl_str_mv Instituto Nacional de Astrofísica, Óptica y Electrónica
dc.source.none.fl_str_mv reponame:Repositorio Institucional del INAOE
instname:Instituto Nacional de Astrofísica, Óptica y Electrónica
instacron:INAOE
instname_str Instituto Nacional de Astrofísica, Óptica y Electrónica
instacron_str INAOE
institution INAOE
reponame_str Repositorio Institucional del INAOE
collection Repositorio Institucional del INAOE
repository.name.fl_str_mv
repository.mail.fl_str_mv
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