Systems for fractional sampling rate conversion
This thesis treats the design of decimation filters for fractional sampling rate conversion system, applicable for Software Radio (SR). We first present a general introduction of Software Radio technology along with the brief description of radio system architecture, multirate techniques, and progra...
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| Tipo de recurso: | tesis de maestría |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2007 |
| País: | México |
| Institución: | Instituto Nacional de Astrofísica, Óptica y Electrónica |
| Repositorio: | Repositorio Institucional del INAOE |
| Idioma: | inglés |
| OAI Identifier: | oai:inaoe.repositorioinstitucional.mx:1009/645 |
| Acceso en línea: | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/645 |
| Access Level: | acceso abierto |
| Palabra clave: | info:eu-repo/classification/Radio de software/Software radio info:eu-repo/classification/Chips de procesamiento de señales digitales/Digital signal processing chips info:eu-repo/classification/Comunicación digital/Digital communication info:eu-repo/classification/cti/1 info:eu-repo/classification/cti/22 info:eu-repo/classification/cti/2203 info:eu-repo/classification/cti/330706 |
| Sumario: | This thesis treats the design of decimation filters for fractional sampling rate conversion system, applicable for Software Radio (SR). We first present a general introduction of Software Radio technology along with the brief description of radio system architecture, multirate techniques, and programmable logic devices (PLDs). Then, the basic principles of Sampling Rate Conversion (SRC) is presented, including various methods for decimation and their impacts on the filter complexity. Further, a review of the Finite Impulse Response (FIR) filters has been done, along with the methods of rounding and sharpening for efficient filter design. The raising technique, block filtering and time varying polyphase structures are also revised. Overview of existing sampling rate conversion filters has been presented, which includes Cascaded Integrated Comb (CIC) filter, Polynomial filter and Time Varying CIC filter. Using multirate techniques and polyphase representation, a simple method of designing fractional sampling rate conversion system based on the Interpolated Finite Impulse Response (IFIR) filter has been proposed. Finally, the proposed algorithm is simulated in MATLAB and implemented in the SPARTAN 3 family of the Xilinx’s Field Programmable Gate Array (FPGA) using project navigator Xilinx ISE 8.2i. The input and output of the implemented structure is verified in Symphony EDA Sonata 3.1. All the proposed MATLAB functions and VHDL programs are included in Appendix. |
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