Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm

3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm 3T1D memory cells present significant tolerance to high levels of device paramete...

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Detalles Bibliográficos
Autores: Amat Bertran, Esteve, García Almudéver, Carmen, Aymerich, N., Canal Corretger, Ramon|||0000-0003-4542-204X, Rubio Sola, Jose Antonio|||0000-0003-1625-1472
Tipo de recurso: artículo
Fecha de publicación:2014
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/115934
Acceso en línea:https://hdl.handle.net/2117/115934
https://dx.doi.org/10.1016/j.mejo.2013.12.001
Access Level:acceso abierto
Palabra clave:Cache memory
Variability
DRAM
Temperature
CMOS
DESIGN
CACHE
Memòria cau
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
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repository_id_str
spelling Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nmAmat Bertran, EsteveGarcía Almudéver, CarmenAymerich, N.Canal Corretger, Ramon|||0000-0003-4542-204XRubio Sola, Jose Antonio|||0000-0003-1625-1472Cache memoryVariabilityDRAMTemperatureCMOSDESIGNCACHEMemòria cauÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that when variability is considered the write access transistor becomes a significant detrimental element on the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some valid strategies in order to mitigate the 3T1D cell variability.Peer Reviewed20142014-10-0120182018-04-04journal articlehttp://purl.org/coar/resource_type/c_6501AMhttp://purl.org/coar/version/c_ab4af688f83e57aainfo:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/2117/115934https://dx.doi.org/10.1016/j.mejo.2013.12.001reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)InglésengMinisterio de Ciencia e Innovación http://doi.org/10.13039/501100004837 TEC2008-01856 PRINCIPIOS DE DISEÑO Y TEST DE SISTEMAS INTEGRADOS EN TERA-ESCALAMinisterio de Ciencia e Innovación http://doi.org/10.13039/501100004837 TIN2010-18368 MICROARQUITECTURA Y COMPILADORES PARA FUTUROS PROCESADORES IIopen accesshttp://purl.org/coar/access_right/c_abf2Attribution-NonCommercial-NoDerivs 3.0 Spainhttp://creativecommons.org/licenses/by-nc-nd/3.0/es/info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/1159342026-05-27T15:37:01Z
dc.title.none.fl_str_mv Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm
title Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm
spellingShingle Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm
Amat Bertran, Esteve
Cache memory
Variability
DRAM
Temperature
CMOS
DESIGN
CACHE
Memòria cau
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
title_short Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm
title_full Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm
title_fullStr Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm
title_full_unstemmed Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm
title_sort Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm
dc.creator.none.fl_str_mv Amat Bertran, Esteve
García Almudéver, Carmen
Aymerich, N.
Canal Corretger, Ramon|||0000-0003-4542-204X
Rubio Sola, Jose Antonio|||0000-0003-1625-1472
author Amat Bertran, Esteve
author_facet Amat Bertran, Esteve
García Almudéver, Carmen
Aymerich, N.
Canal Corretger, Ramon|||0000-0003-4542-204X
Rubio Sola, Jose Antonio|||0000-0003-1625-1472
author_role author
author2 García Almudéver, Carmen
Aymerich, N.
Canal Corretger, Ramon|||0000-0003-4542-204X
Rubio Sola, Jose Antonio|||0000-0003-1625-1472
author2_role author
author
author
author
dc.subject.none.fl_str_mv Cache memory
Variability
DRAM
Temperature
CMOS
DESIGN
CACHE
Memòria cau
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
topic Cache memory
Variability
DRAM
Temperature
CMOS
DESIGN
CACHE
Memòria cau
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
description 3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that when variability is considered the write access transistor becomes a significant detrimental element on the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some valid strategies in order to mitigate the 3T1D cell variability.
publishDate 2014
dc.date.none.fl_str_mv 2014
2014-10-01
2018
2018-04-04
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
AM
http://purl.org/coar/version/c_ab4af688f83e57aa
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/115934
https://dx.doi.org/10.1016/j.mejo.2013.12.001
url https://hdl.handle.net/2117/115934
https://dx.doi.org/10.1016/j.mejo.2013.12.001
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.relation.none.fl_str_mv Ministerio de Ciencia e Innovación http://doi.org/10.13039/501100004837 TEC2008-01856 PRINCIPIOS DE DISEÑO Y TEST DE SISTEMAS INTEGRADOS EN TERA-ESCALA
Ministerio de Ciencia e Innovación http://doi.org/10.13039/501100004837 TIN2010-18368 MICROARQUITECTURA Y COMPILADORES PARA FUTUROS PROCESADORES II
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
Attribution-NonCommercial-NoDerivs 3.0 Spain
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
Attribution-NonCommercial-NoDerivs 3.0 Spain
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,301603

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