Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm
3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm 3T1D memory cells present significant tolerance to high levels of device paramete...
| Autores: | , , , , |
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| Tipo de documento: | artigo |
| Data de publicação: | 2014 |
| País: | España |
| Recursos: | Universitat Politècnica de Catalunya (UPC) |
| Repositório: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglês |
| OAI Identifier: | oai:upcommons.upc.edu:2117/115934 |
| Acesso em linha: | https://hdl.handle.net/2117/115934 https://dx.doi.org/10.1016/j.mejo.2013.12.001 |
| Access Level: | Acceso aberto |
| Palavra-chave: | Cache memory Variability DRAM Temperature CMOS DESIGN CACHE Memòria cau Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
| Resumo: | 3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that when variability is considered the write access transistor becomes a significant detrimental element on the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some valid strategies in order to mitigate the 3T1D cell variability. |
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