Architecture, RTL implementation and verification of the MIPI CSI-2/D-PHY transmitter version 1.2/1.3

This thesis explores the implementation of the Mobile Industry Processor Interface (MIPI) Camera Serial Interface 2 (CSI-2) and the D-PHY physical layer, which are critical in modern camera systems for mobile and embedded devices. The primary objective of this project is the design, implementation a...

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Detalles Bibliográficos
Autor: Zhu Wang, Shexing
Tipo de recurso: tesis de maestría
Fecha de publicación:2024
País:España
Institución:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/424639
Acceso en línea:https://hdl.handle.net/2117/424639
Access Level:acceso embargado
Palabra clave:Application-specific integrated circuits
Embedded computer systems
Computer network protocols
ASIC
MIPI
FPGA
Image sensor
Circuits integrats d'aplicació específica
Sistemes incrustats (Informàtica)
Protocols de xarxes d'ordinadors
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
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spelling Architecture, RTL implementation and verification of the MIPI CSI-2/D-PHY transmitter version 1.2/1.3Zhu Wang, ShexingApplication-specific integrated circuitsEmbedded computer systemsComputer network protocolsASICMIPIFPGAImage sensorCircuits integrats d'aplicació específicaSistemes incrustats (Informàtica)Protocols de xarxes d'ordinadorsÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integratsThis thesis explores the implementation of the Mobile Industry Processor Interface (MIPI) Camera Serial Interface 2 (CSI-2) and the D-PHY physical layer, which are critical in modern camera systems for mobile and embedded devices. The primary objective of this project is the design, implementation and verification of the MIPI CSI-2 protocol and D-PHY layer. The thesis details the development process of this application-specific integrated circuit (ASIC), including the design of the modified architecture, the usage of the Universal Verification Methodology (UVM) for simulation and validation of the design in field programmable gate arrays (FPGA) for loopback testing using Xilinx MIPI receiver IP. Simulation results demonstrate the feasibility of the proposed architecture in reaching a higher bitrate per data lane compared to the standard architecture. Furthermore, the thesis discusses the synthesis and place and route (PnR) aspects of the design targeting 180 nm technology and 75 MHz clock frequency.Universitat Politècnica de CatalunyaMateo Peña, Diego20242024-09-1320252025-02-1920302030-02-19master thesishttp://purl.org/coar/resource_type/c_bdccNAhttp://purl.org/coar/version/c_be7fb7dd8ff6fe43info:eu-repo/semantics/masterThesisapplication/pdfhttps://hdl.handle.net/2117/424639reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengembargoed accesshttp://purl.org/coar/access_right/c_f1cfinfo:eu-repo/semantics/embargoedAccessoai:upcommons.upc.edu:2117/4246392026-05-27T15:37:01Z
dc.title.none.fl_str_mv Architecture, RTL implementation and verification of the MIPI CSI-2/D-PHY transmitter version 1.2/1.3
title Architecture, RTL implementation and verification of the MIPI CSI-2/D-PHY transmitter version 1.2/1.3
spellingShingle Architecture, RTL implementation and verification of the MIPI CSI-2/D-PHY transmitter version 1.2/1.3
Zhu Wang, Shexing
Application-specific integrated circuits
Embedded computer systems
Computer network protocols
ASIC
MIPI
FPGA
Image sensor
Circuits integrats d'aplicació específica
Sistemes incrustats (Informàtica)
Protocols de xarxes d'ordinadors
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
title_short Architecture, RTL implementation and verification of the MIPI CSI-2/D-PHY transmitter version 1.2/1.3
title_full Architecture, RTL implementation and verification of the MIPI CSI-2/D-PHY transmitter version 1.2/1.3
title_fullStr Architecture, RTL implementation and verification of the MIPI CSI-2/D-PHY transmitter version 1.2/1.3
title_full_unstemmed Architecture, RTL implementation and verification of the MIPI CSI-2/D-PHY transmitter version 1.2/1.3
title_sort Architecture, RTL implementation and verification of the MIPI CSI-2/D-PHY transmitter version 1.2/1.3
dc.creator.none.fl_str_mv Zhu Wang, Shexing
author Zhu Wang, Shexing
author_facet Zhu Wang, Shexing
author_role author
dc.contributor.none.fl_str_mv Mateo Peña, Diego
dc.subject.none.fl_str_mv Application-specific integrated circuits
Embedded computer systems
Computer network protocols
ASIC
MIPI
FPGA
Image sensor
Circuits integrats d'aplicació específica
Sistemes incrustats (Informàtica)
Protocols de xarxes d'ordinadors
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
topic Application-specific integrated circuits
Embedded computer systems
Computer network protocols
ASIC
MIPI
FPGA
Image sensor
Circuits integrats d'aplicació específica
Sistemes incrustats (Informàtica)
Protocols de xarxes d'ordinadors
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
description This thesis explores the implementation of the Mobile Industry Processor Interface (MIPI) Camera Serial Interface 2 (CSI-2) and the D-PHY physical layer, which are critical in modern camera systems for mobile and embedded devices. The primary objective of this project is the design, implementation and verification of the MIPI CSI-2 protocol and D-PHY layer. The thesis details the development process of this application-specific integrated circuit (ASIC), including the design of the modified architecture, the usage of the Universal Verification Methodology (UVM) for simulation and validation of the design in field programmable gate arrays (FPGA) for loopback testing using Xilinx MIPI receiver IP. Simulation results demonstrate the feasibility of the proposed architecture in reaching a higher bitrate per data lane compared to the standard architecture. Furthermore, the thesis discusses the synthesis and place and route (PnR) aspects of the design targeting 180 nm technology and 75 MHz clock frequency.
publishDate 2024
dc.date.none.fl_str_mv 2024
2024-09-13
2025
2025-02-19
2030
2030-02-19
dc.type.none.fl_str_mv master thesis
http://purl.org/coar/resource_type/c_bdcc
NA
http://purl.org/coar/version/c_be7fb7dd8ff6fe43
dc.type.openaire.fl_str_mv info:eu-repo/semantics/masterThesis
format masterThesis
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/424639
url https://hdl.handle.net/2117/424639
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv embargoed access
http://purl.org/coar/access_right/c_f1cf
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/embargoedAccess
rights_invalid_str_mv embargoed access
http://purl.org/coar/access_right/c_f1cf
eu_rights_str_mv embargoedAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Universitat Politècnica de Catalunya
publisher.none.fl_str_mv Universitat Politècnica de Catalunya
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15.811543

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