Architecture, RTL implementation and verification of the MIPI CSI-2/D-PHY transmitter version 1.2/1.3
This thesis explores the implementation of the Mobile Industry Processor Interface (MIPI) Camera Serial Interface 2 (CSI-2) and the D-PHY physical layer, which are critical in modern camera systems for mobile and embedded devices. The primary objective of this project is the design, implementation a...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2024 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/424639 |
| Acceso en línea: | https://hdl.handle.net/2117/424639 |
| Access Level: | acceso embargado |
| Palabra clave: | Application-specific integrated circuits Embedded computer systems Computer network protocols ASIC MIPI FPGA Image sensor Circuits integrats d'aplicació específica Sistemes incrustats (Informàtica) Protocols de xarxes d'ordinadors Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
| Sumario: | This thesis explores the implementation of the Mobile Industry Processor Interface (MIPI) Camera Serial Interface 2 (CSI-2) and the D-PHY physical layer, which are critical in modern camera systems for mobile and embedded devices. The primary objective of this project is the design, implementation and verification of the MIPI CSI-2 protocol and D-PHY layer. The thesis details the development process of this application-specific integrated circuit (ASIC), including the design of the modified architecture, the usage of the Universal Verification Methodology (UVM) for simulation and validation of the design in field programmable gate arrays (FPGA) for loopback testing using Xilinx MIPI receiver IP. Simulation results demonstrate the feasibility of the proposed architecture in reaching a higher bitrate per data lane compared to the standard architecture. Furthermore, the thesis discusses the synthesis and place and route (PnR) aspects of the design targeting 180 nm technology and 75 MHz clock frequency. |
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