Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs

Detalles Bibliográficos
Autores: Rodríguez Medina, Alfonso|||0000-0001-6326-743X, Otero Marnotes, José Andrés|||0000-0003-4995-7009, Platzner, Marco|||0000-0002-6893-063X, Torre Arnanz, Eduardo de la|||0000-0001-5697-0573
Tipo de recurso: artículo
Fecha de publicación:2022
País:España
Institución:Universidad Politécnica de Madrid
Repositorio:Archivo Digital UPM
OAI Identifier:oai:oa.upm.es:87621
Acceso en línea:https://oa.upm.es/87621/
Access Level:acceso abierto
Palabra clave:ARCHITECTURE
Computational modeling
Computer architecture
data-level parallelism
edge computing
Edge intelligence
evolvable hardware
multithreading
NEURAL-NETWORKS
Parallel processing
Reconfigurable Computing
software
Tools
computational modeling
Computer Architecture
Edge computing
Evolvable hardware
Field programmable gate arrays
parallel processing
PROGRAMMING-MODELS
Reconfigurable computing
Software
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repository_id_str
spelling Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAsRodríguez Medina, Alfonso|||0000-0001-6326-743XOtero Marnotes, José Andrés|||0000-0003-4995-7009Platzner, Marco|||0000-0002-6893-063XTorre Arnanz, Eduardo de la|||0000-0001-5697-0573ARCHITECTUREComputational modelingComputer architecturedata-level parallelismedge computingEdge intelligenceevolvable hardwaremultithreadingNEURAL-NETWORKSParallel processingReconfigurable ComputingsoftwareToolscomputational modelingComputer Architecturedata-level parallelismEdge computingEdge intelligenceEvolvable hardwareField programmable gate arraysmultithreadingparallel processingPROGRAMMING-MODELSReconfigurable computingSoftware20222022-01-01journal articlehttp://purl.org/coar/resource_type/c_6501info:eu-repo/semantics/articlehttps://oa.upm.es/87621/reponame:Archivo Digital UPMinstname:Universidad Politécnica de MadridInglésenopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:oa.upm.es:876212026-06-21T12:45:07Z
dc.title.none.fl_str_mv Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs
title Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs
spellingShingle Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs
Rodríguez Medina, Alfonso|||0000-0001-6326-743X
ARCHITECTURE
Computational modeling
Computer architecture
data-level parallelism
edge computing
Edge intelligence
evolvable hardware
multithreading
NEURAL-NETWORKS
Parallel processing
Reconfigurable Computing
software
Tools
computational modeling
Computer Architecture
data-level parallelism
Edge computing
Edge intelligence
Evolvable hardware
Field programmable gate arrays
multithreading
parallel processing
PROGRAMMING-MODELS
Reconfigurable computing
Software
title_short Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs
title_full Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs
title_fullStr Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs
title_full_unstemmed Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs
title_sort Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs
dc.creator.none.fl_str_mv Rodríguez Medina, Alfonso|||0000-0001-6326-743X
Otero Marnotes, José Andrés|||0000-0003-4995-7009
Platzner, Marco|||0000-0002-6893-063X
Torre Arnanz, Eduardo de la|||0000-0001-5697-0573
author Rodríguez Medina, Alfonso|||0000-0001-6326-743X
author_facet Rodríguez Medina, Alfonso|||0000-0001-6326-743X
Otero Marnotes, José Andrés|||0000-0003-4995-7009
Platzner, Marco|||0000-0002-6893-063X
Torre Arnanz, Eduardo de la|||0000-0001-5697-0573
author_role author
author2 Otero Marnotes, José Andrés|||0000-0003-4995-7009
Platzner, Marco|||0000-0002-6893-063X
Torre Arnanz, Eduardo de la|||0000-0001-5697-0573
author2_role author
author
author
dc.subject.none.fl_str_mv ARCHITECTURE
Computational modeling
Computer architecture
data-level parallelism
edge computing
Edge intelligence
evolvable hardware
multithreading
NEURAL-NETWORKS
Parallel processing
Reconfigurable Computing
software
Tools
computational modeling
Computer Architecture
data-level parallelism
Edge computing
Edge intelligence
Evolvable hardware
Field programmable gate arrays
multithreading
parallel processing
PROGRAMMING-MODELS
Reconfigurable computing
Software
topic ARCHITECTURE
Computational modeling
Computer architecture
data-level parallelism
edge computing
Edge intelligence
evolvable hardware
multithreading
NEURAL-NETWORKS
Parallel processing
Reconfigurable Computing
software
Tools
computational modeling
Computer Architecture
data-level parallelism
Edge computing
Edge intelligence
Evolvable hardware
Field programmable gate arrays
multithreading
parallel processing
PROGRAMMING-MODELS
Reconfigurable computing
Software
publishDate 2022
dc.date.none.fl_str_mv 2022
2022-01-01
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://oa.upm.es/87621/
url https://oa.upm.es/87621/
dc.language.none.fl_str_mv Inglés
en
language_invalid_str_mv Inglés
en
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.source.none.fl_str_mv reponame:Archivo Digital UPM
instname:Universidad Politécnica de Madrid
instname_str Universidad Politécnica de Madrid
reponame_str Archivo Digital UPM
collection Archivo Digital UPM
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869420278151380992
score 15.81155

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