Power profiling-guided floorplanner for 3D multi-processor systems-on-chip

Three-dimensional (3D) integration has become one of the most promising techniques for the development of future multi-core processors, since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems because the cl...

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Detalles Bibliográficos
Autores: Arnaldo, Ignacio, Higalgo, J. Ignacio, Risco Martín, José Luis, Ayala Rodrigo, José Luis
Tipo de recurso: artículo
Fecha de publicación:2012
País:España
Institución:Universidad Complutense de Madrid (UCM)
Repositorio:Docta Complutense
Idioma:inglés
OAI Identifier:oai:docta.ucm.es:20.500.14352/119961
Acceso en línea:https://hdl.handle.net/20.500.14352/119961
Access Level:acceso abierto
Palabra clave:Hardware
3304.06 Arquitectura de Ordenadores
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spelling Power profiling-guided floorplanner for 3D multi-processor systems-on-chipArnaldo, IgnacioHigalgo, J. IgnacioRisco Martín, José LuisAyala Rodrigo, José LuisHardware3304.06 Arquitectura de OrdenadoresThree-dimensional (3D) integration has become one of the most promising techniques for the development of future multi-core processors, since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems because the closer proximity of heat generating dies makes existing thermal hotspots more severe. Thermal-aware floorplanners can play an important role to improve the thermal profile, but they have failed in considering the dynamic power profiles of the applications. This study proposes a novel thermal-aware floorplanner guided by the power profiling of a set of benchmarks that are representative of the application scope. The results show how our approach outperforms the thermal metrics as compared with the worst-case scenario usually considered in ‘traditional’ thermal-aware floorplanners.The Institution of Engineering and TechnologyUniversidad Complutense de Madrid20122012-01-0120122012-01-01journal articlehttp://purl.org/coar/resource_type/c_6501info:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/20.500.14352/119961reponame:Docta Complutenseinstname:Universidad Complutense de Madrid (UCM)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2Attribution 4.0 Internationalhttp://creativecommons.org/licenses/by/4.0/info:eu-repo/semantics/openAccessoai:docta.ucm.es:20.500.14352/1199612026-06-02T12:44:21Z
dc.title.none.fl_str_mv Power profiling-guided floorplanner for 3D multi-processor systems-on-chip
title Power profiling-guided floorplanner for 3D multi-processor systems-on-chip
spellingShingle Power profiling-guided floorplanner for 3D multi-processor systems-on-chip
Arnaldo, Ignacio
Hardware
3304.06 Arquitectura de Ordenadores
title_short Power profiling-guided floorplanner for 3D multi-processor systems-on-chip
title_full Power profiling-guided floorplanner for 3D multi-processor systems-on-chip
title_fullStr Power profiling-guided floorplanner for 3D multi-processor systems-on-chip
title_full_unstemmed Power profiling-guided floorplanner for 3D multi-processor systems-on-chip
title_sort Power profiling-guided floorplanner for 3D multi-processor systems-on-chip
dc.creator.none.fl_str_mv Arnaldo, Ignacio
Higalgo, J. Ignacio
Risco Martín, José Luis
Ayala Rodrigo, José Luis
author Arnaldo, Ignacio
author_facet Arnaldo, Ignacio
Higalgo, J. Ignacio
Risco Martín, José Luis
Ayala Rodrigo, José Luis
author_role author
author2 Higalgo, J. Ignacio
Risco Martín, José Luis
Ayala Rodrigo, José Luis
author2_role author
author
author
dc.contributor.none.fl_str_mv Universidad Complutense de Madrid
dc.subject.none.fl_str_mv Hardware
3304.06 Arquitectura de Ordenadores
topic Hardware
3304.06 Arquitectura de Ordenadores
description Three-dimensional (3D) integration has become one of the most promising techniques for the development of future multi-core processors, since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems because the closer proximity of heat generating dies makes existing thermal hotspots more severe. Thermal-aware floorplanners can play an important role to improve the thermal profile, but they have failed in considering the dynamic power profiles of the applications. This study proposes a novel thermal-aware floorplanner guided by the power profiling of a set of benchmarks that are representative of the application scope. The results show how our approach outperforms the thermal metrics as compared with the worst-case scenario usually considered in ‘traditional’ thermal-aware floorplanners.
publishDate 2012
dc.date.none.fl_str_mv 2012
2012-01-01
2012
2012-01-01
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/20.500.14352/119961
url https://hdl.handle.net/20.500.14352/119961
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
Attribution 4.0 International
http://creativecommons.org/licenses/by/4.0/
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
Attribution 4.0 International
http://creativecommons.org/licenses/by/4.0/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv The Institution of Engineering and Technology
publisher.none.fl_str_mv The Institution of Engineering and Technology
dc.source.none.fl_str_mv reponame:Docta Complutense
instname:Universidad Complutense de Madrid (UCM)
instname_str Universidad Complutense de Madrid (UCM)
reponame_str Docta Complutense
collection Docta Complutense
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15.811543

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