Cita APA

Arnaldo, I., Higalgo, J. I., Risco Martín, J. L., & Ayala Rodrigo, J. L. (2012). Power profiling-guided floorplanner for 3D multi-processor systems-on-chip.

Citación estilo Chicago

Arnaldo, Ignacio, J. Ignacio Higalgo, José Luis Risco Martín, y José Luis Ayala Rodrigo. Power Profiling-guided Floorplanner for 3D Multi-processor Systems-on-chip. 2012.

Cita MLA

Arnaldo, Ignacio, J. Ignacio Higalgo, José Luis Risco Martín, y José Luis Ayala Rodrigo. Power Profiling-guided Floorplanner for 3D Multi-processor Systems-on-chip. 2012.