Power profiling-guided floorplanner for 3D multi-processor systems-on-chip
Three-dimensional (3D) integration has become one of the most promising techniques for the development of future multi-core processors, since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems because the cl...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2012 |
| País: | España |
| Institución: | Universidad Complutense de Madrid (UCM) |
| Repositorio: | Docta Complutense |
| Idioma: | inglés |
| OAI Identifier: | oai:docta.ucm.es:20.500.14352/119961 |
| Acceso en línea: | https://hdl.handle.net/20.500.14352/119961 |
| Access Level: | acceso abierto |
| Palabra clave: | Hardware 3304.06 Arquitectura de Ordenadores |
| Sumario: | Three-dimensional (3D) integration has become one of the most promising techniques for the development of future multi-core processors, since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems because the closer proximity of heat generating dies makes existing thermal hotspots more severe. Thermal-aware floorplanners can play an important role to improve the thermal profile, but they have failed in considering the dynamic power profiles of the applications. This study proposes a novel thermal-aware floorplanner guided by the power profiling of a set of benchmarks that are representative of the application scope. The results show how our approach outperforms the thermal metrics as compared with the worst-case scenario usually considered in ‘traditional’ thermal-aware floorplanners. |
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