Towards a Reliable PUF Using Organic Thin-Film Transistors
As printed electronics continue to evolve, Organic Thin Film Transistors (OTFTs) still present high process-induced variability. Paradoxically, this feature can be used for security purposes. Specifically, Physical Unclonable Functions (PUFs) that provide cryptographic keys for low-cost, resource-co...
| Autores: | , , , , , , |
|---|---|
| Tipo de documento: | capítulo de livro |
| Data de publicação: | 2025 |
| País: | España |
| Recursos: | Universitat Autònoma de Barcelona |
| Repositório: | Dipòsit Digital de Documents de la UAB |
| Idioma: | inglês |
| OAI Identifier: | oai:ddd.uab.cat:320846 |
| Acesso em linha: | https://ddd.uab.cat/record/320846 https://dx.doi.org/urn:doi:10.1109/SMACD65553.2025.11091991 |
| Access Level: | Acesso embargado |
| Palavra-chave: | Bit Selection Optimization OTFT PUF Reliability |
| Resumo: | As printed electronics continue to evolve, Organic Thin Film Transistors (OTFTs) still present high process-induced variability. Paradoxically, this feature can be used for security purposes. Specifically, Physical Unclonable Functions (PUFs) that provide cryptographic keys for low-cost, resource-constrained applications take advantage of this. However, the reliability of OTFT-based PUFs remains a significant challenge, as thermal annealing, bias stress, and the passage of time (even after being powered off) can introduce instabilities, thus altering the cryptographic keys they generate. To address this issue, we have successfully implemented an optimization-based bit selection approach to enhance their reliability. Our evaluation considers reliability holistically, accounting for thermal annealing, bias stress, and off time degradations. The results demonstrate that by strategically optimizing challenge-response pair selection, the integrity of the generated keys is not compromised. In this work, the feasibility of OTFT-based PUFs and the solutions to key limitations are presented as a step towards improving the practicality and robustness of security solutions for printed electronics. |
|---|