An efficient NB-LDPC decoder architecture for space telecommand links

In the framework of error correction in space telecommand (TC) links, the Consultative Committee for Space Data Systems (CCSDS) currently recommends short block-length BCH and binary low-density parity-check (LDPC) codes. Other alternatives have been discarded due to their high decoding complexity,...

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Autores: Álvarez Ruiz, Ángel, Fernández Solórzano, Víctor Manuel|||0000-0003-0614-151X, Matuz, Balázs
Tipo de documento: artigo
Data de publicação:2021
País:España
Recursos:Universidad de Cantabria (UC)
Repositório:UCrea Repositorio Abierto de la Universidad de Cantabria
Idioma:inglês
OAI Identifier:oai:repositorio.unican.es:10902/21161
Acesso em linha:http://hdl.handle.net/10902/21161
Access Level:Acceso aberto
Palavra-chave:VLSI design
FPGA
Non-binary LDPC codes
Decoder architecture
Space communications
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spelling An efficient NB-LDPC decoder architecture for space telecommand linksÁlvarez Ruiz, ÁngelFernández Solórzano, Víctor Manuel|||0000-0003-0614-151XMatuz, BalázsVLSI designFPGANon-binary LDPC codesDecoder architectureSpace communicationsIn the framework of error correction in space telecommand (TC) links, the Consultative Committee for Space Data Systems (CCSDS) currently recommends short block-length BCH and binary low-density parity-check (LDPC) codes. Other alternatives have been discarded due to their high decoding complexity, such as non-binary LDPC (NB-LDPC) codes. NB-LDPC codes perform better than their binary counterparts over AWGN and jamming channels, being great candidates for space communications. We show the feasibility of NB-LDPC coding for space TC applications by proposing a highly efficient decoding architecture. The proposed decoder is implemented for a (128,64) NB-LDPC code over GF(16) and the design is particularized for a space-certified Virtex-5QV FPGA. The results prove that NB-LDPC coding is an alternative that outperforms the standardized binary LDPC, with a coding gain of 0.7 dB at a reasonable implementation cost. Given that the maximum rate for TC recommended by the CCSDS is 2 Mbps, the proposed architecture achieves a throughput of 2.03 Mbps using only 9615 LUTs and 5637 FFs (no dedicated memories are used). In addition, this architecture is suitable for any regular (2,4) NB-LDPC (128,64) code over GF(16) independently of the H matrix, allowing flexibility in the choice of the code. This brief places NB-LDPC codes as the excellent candidates for future versions of the telecommand uplink standard.This work was supported by Spanish MICINN/AEI under Project TEC2017-86722-C4-3-R.Institute of Electrical and Electronics Engineers, Inc.Universidad de Cantabria20212021-04-01journal articlehttp://purl.org/coar/resource_type/c_6501NAhttp://purl.org/coar/version/c_be7fb7dd8ff6fe43info:eu-repo/semantics/articlehttp://hdl.handle.net/10902/21161IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 68(4), 1213-1217reponame:UCrea Repositorio Abierto de la Universidad de Cantabriainstname:Universidad de Cantabria (UC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:repositorio.unican.es:10902/211612026-06-02T12:39:31Z
dc.title.none.fl_str_mv An efficient NB-LDPC decoder architecture for space telecommand links
title An efficient NB-LDPC decoder architecture for space telecommand links
spellingShingle An efficient NB-LDPC decoder architecture for space telecommand links
Álvarez Ruiz, Ángel
VLSI design
FPGA
Non-binary LDPC codes
Decoder architecture
Space communications
title_short An efficient NB-LDPC decoder architecture for space telecommand links
title_full An efficient NB-LDPC decoder architecture for space telecommand links
title_fullStr An efficient NB-LDPC decoder architecture for space telecommand links
title_full_unstemmed An efficient NB-LDPC decoder architecture for space telecommand links
title_sort An efficient NB-LDPC decoder architecture for space telecommand links
dc.creator.none.fl_str_mv Álvarez Ruiz, Ángel
Fernández Solórzano, Víctor Manuel|||0000-0003-0614-151X
Matuz, Balázs
author Álvarez Ruiz, Ángel
author_facet Álvarez Ruiz, Ángel
Fernández Solórzano, Víctor Manuel|||0000-0003-0614-151X
Matuz, Balázs
author_role author
author2 Fernández Solórzano, Víctor Manuel|||0000-0003-0614-151X
Matuz, Balázs
author2_role author
author
dc.contributor.none.fl_str_mv Universidad de Cantabria
dc.subject.none.fl_str_mv VLSI design
FPGA
Non-binary LDPC codes
Decoder architecture
Space communications
topic VLSI design
FPGA
Non-binary LDPC codes
Decoder architecture
Space communications
description In the framework of error correction in space telecommand (TC) links, the Consultative Committee for Space Data Systems (CCSDS) currently recommends short block-length BCH and binary low-density parity-check (LDPC) codes. Other alternatives have been discarded due to their high decoding complexity, such as non-binary LDPC (NB-LDPC) codes. NB-LDPC codes perform better than their binary counterparts over AWGN and jamming channels, being great candidates for space communications. We show the feasibility of NB-LDPC coding for space TC applications by proposing a highly efficient decoding architecture. The proposed decoder is implemented for a (128,64) NB-LDPC code over GF(16) and the design is particularized for a space-certified Virtex-5QV FPGA. The results prove that NB-LDPC coding is an alternative that outperforms the standardized binary LDPC, with a coding gain of 0.7 dB at a reasonable implementation cost. Given that the maximum rate for TC recommended by the CCSDS is 2 Mbps, the proposed architecture achieves a throughput of 2.03 Mbps using only 9615 LUTs and 5637 FFs (no dedicated memories are used). In addition, this architecture is suitable for any regular (2,4) NB-LDPC (128,64) code over GF(16) independently of the H matrix, allowing flexibility in the choice of the code. This brief places NB-LDPC codes as the excellent candidates for future versions of the telecommand uplink standard.
publishDate 2021
dc.date.none.fl_str_mv 2021
2021-04-01
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
NA
http://purl.org/coar/version/c_be7fb7dd8ff6fe43
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv http://hdl.handle.net/10902/21161
url http://hdl.handle.net/10902/21161
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers, Inc.
publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers, Inc.
dc.source.none.fl_str_mv IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 68(4), 1213-1217
reponame:UCrea Repositorio Abierto de la Universidad de Cantabria
instname:Universidad de Cantabria (UC)
instname_str Universidad de Cantabria (UC)
reponame_str UCrea Repositorio Abierto de la Universidad de Cantabria
collection UCrea Repositorio Abierto de la Universidad de Cantabria
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15.301603

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